Changed armv7m and cortexm3 to use nev arm_adi_v5 instead of cortex_swjdp.
Added support for accessport ROM table identification, dap command. git-svn-id: svn://svn.berlios.de/openocd/trunk@1536 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
mlu
parent
573d9a0368
commit
b0d04ab6c6
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@ -11,12 +11,12 @@ AM_CPPFLAGS = -DPKGLIBDIR=\"$(pkglibdir)\" @CPPFLAGS@
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noinst_LIBRARIES = libtarget.a
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libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
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arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
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arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c \
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arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c arm_adi_v5.c \
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etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
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mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
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noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
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arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
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arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
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arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h arm_adi_v5.h \
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etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
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nobase_dist_pkglib_DATA =
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@ -550,6 +550,12 @@ int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
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int armv7m_register_commands(struct command_context_s *cmd_ctx)
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{
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command_t *arm_adi_v5_dap_cmd;
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arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
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register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "dap info for ap [num] (default 0)");
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register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "select a different AP [num] (default 0)");
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return ERROR_OK;
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}
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@ -695,3 +701,45 @@ int armv7m_blank_check_memory(struct target_s *target, u32 address, u32 count, u
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return ERROR_OK;
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}
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int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv7m_common_t *armv7m = target->arch_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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u32 apsel, apid;
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int retval;
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apsel = 0;
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if (argc > 0)
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{
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apsel = strtoul(args[0], NULL, 0);
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}
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dap_ap_select(swjdp, apsel);
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dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
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retval = swjdp_transaction_endcheck(swjdp);
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command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid);
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return retval;
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}
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int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
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target_t *target = get_current_target(cmd_ctx);
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armv7m_common_t *armv7m = target->arch_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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int retval;
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u32 apsel;
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apsel = 0;
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if (argc > 0)
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{
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apsel = strtoul(args[0], NULL, 0);
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}
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retval = dap_info_command(cmd_ctx, swjdp, apsel);
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return retval;
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}
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@ -29,6 +29,7 @@
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#include "register.h"
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#include "target.h"
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#include "arm_jtag.h"
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#include "arm_adi_v5.h"
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/* define for enabling armv7 gdb workarounds */
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#if 1
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@ -78,6 +79,8 @@ typedef struct armv7m_common_s
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reg_cache_t *core_cache;
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enum armv7m_mode core_mode;
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int exception_number;
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swjdp_common_t swjdp_info;
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/* Direct processor core register read and writes */
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int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
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@ -22,6 +22,10 @@
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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* *
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* Cortex-M3(tm) TRM, ARM DDI 0337C *
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* *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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@ -101,19 +105,70 @@ target_type_t cortexm3_target =
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.quit = cortex_m3_quit
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};
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int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
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{
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int retval;
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u32 dcrdr;
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/* because the DCB_DCRDR is used for the emulated dcc channel
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* we gave to save/restore the DCB_DCRDR when used */
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mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
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dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
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dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum );
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/* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
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dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
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dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
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mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
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retval = swjdp_transaction_endcheck(swjdp);
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return retval;
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}
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int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
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{
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int retval;
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u32 dcrdr;
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/* because the DCB_DCRDR is used for the emulated dcc channel
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* we gave to save/restore the DCB_DCRDR when used */
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mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
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swjdp->trans_mode = TRANS_MODE_COMPOSITE;
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/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
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dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
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dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
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/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
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dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
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dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
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mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
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retval = swjdp_transaction_endcheck(swjdp);
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return retval;
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}
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int cortex_m3_write_debug_halt_mask(target_t *target, u32 mask_on, u32 mask_off)
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{
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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/* mask off status bits */
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cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
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/* create new register mask */
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cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
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return ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
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return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
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}
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int cortex_m3_clear_halt(target_t *target)
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@ -121,15 +176,15 @@ int cortex_m3_clear_halt(target_t *target)
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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/* clear step if any */
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cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
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/* Read Debug Fault Status Register */
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ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
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mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
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/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
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ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
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mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
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LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
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return ERROR_OK;
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@ -140,7 +195,7 @@ int cortex_m3_single_step_core(target_t *target)
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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u32 dhcsr_save;
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/* backup dhcsr reg */
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@ -148,8 +203,8 @@ int cortex_m3_single_step_core(target_t *target)
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/* mask interrupts if not done already */
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if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
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ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
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ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
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mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
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mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
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LOG_DEBUG(" ");
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/* restore dhcsr reg */
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@ -163,17 +218,16 @@ int cortex_m3_exec_opcode(target_t *target,u32 opcode, int len /* MODE, r0_inval
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{
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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u32 savedram;
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int retvalue;
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ahbap_read_system_u32(swjdp, 0x20000000, &savedram);
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ahbap_write_system_u32(swjdp, 0x20000000, opcode);
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ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
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mem_ap_read_u32(swjdp, 0x20000000, &savedram);
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mem_ap_write_u32(swjdp, 0x20000000, opcode);
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cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15);
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cortex_m3_single_step_core(target);
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armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
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retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram);
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retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram);
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return retvalue;
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}
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@ -200,28 +254,28 @@ int cortex_m3_endreset_event(target_t *target)
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
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cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
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ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
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mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
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LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
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/* this regsiter is used for emulated dcc channel */
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ahbap_write_system_u32(swjdp, DCB_DCRDR, 0);
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mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
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/* Enable debug requests */
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ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
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mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
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if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
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ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
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mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
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/* clear any interrupt masking */
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cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
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/* Enable trace and dwt */
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ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
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mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
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/* Monitor bus faults */
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ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
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mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
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/* Enable FPB */
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target_write_u32(target, FP_CTRL, 3);
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@ -245,7 +299,7 @@ int cortex_m3_endreset_event(target_t *target)
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armv7m_invalidate_core_regs(target);
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/* make sure we have latest dhcsr flags */
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ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
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mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
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return ERROR_OK;
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}
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@ -283,36 +337,35 @@ int cortex_m3_examine_exception_reason(target_t *target)
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/* get pointers to arch-specific information */
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armv7m_common_t *armv7m = target->arch_info;
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cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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swjdp_common_t *swjdp = &armv7m->swjdp_info;
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ahbap_read_system_u32(swjdp, NVIC_SHCSR, &shcsr);
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mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
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switch (armv7m->exception_number)
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{
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case 2: /* NMI */
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break;
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case 3: /* Hard Fault */
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ahbap_read_system_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
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mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
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if (except_sr & 0x40000000)
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{
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ahbap_read_system_u32(swjdp, NVIC_CFSR, &cfsr);
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mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
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}
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break;
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case 4: /* Memory Management */
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ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
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ahbap_read_system_u32(swjdp, NVIC_MMFAR, &except_ar);
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mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
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mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
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break;
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case 5: /* Bus Fault */
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ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
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ahbap_read_system_u32(swjdp, NVIC_BFAR, &except_ar);
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mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
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mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
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break;
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case 6: /* Usage Fault */
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ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
|
||||
mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
|
||||
break;
|
||||
case 11: /* SVCall */
|
||||
break;
|
||||
case 12: /* Debug Monitor */
|
||||
ahbap_read_system_u32(swjdp, NVIC_DFSR, &except_sr);
|
||||
mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
|
||||
break;
|
||||
case 14: /* PendSV */
|
||||
break;
|
||||
|
|
@ -337,14 +390,14 @@ int cortex_m3_debug_entry(target_t *target)
|
|||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
|
||||
LOG_DEBUG(" ");
|
||||
if (armv7m->pre_debug_entry)
|
||||
armv7m->pre_debug_entry(target);
|
||||
|
||||
cortex_m3_clear_halt(target);
|
||||
ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
|
||||
if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
|
||||
return retval;
|
||||
|
|
@ -417,10 +470,10 @@ int cortex_m3_poll(target_t *target)
|
|||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
|
||||
/* Read from Debug Halting Control and Status Register */
|
||||
retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
if (retval != ERROR_OK)
|
||||
{
|
||||
target->state = TARGET_UNKNOWN;
|
||||
|
|
@ -430,7 +483,7 @@ int cortex_m3_poll(target_t *target)
|
|||
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
|
||||
{
|
||||
/* check if still in reset */
|
||||
ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
|
||||
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
|
||||
{
|
||||
|
|
@ -476,7 +529,7 @@ int cortex_m3_poll(target_t *target)
|
|||
|
||||
#if 0
|
||||
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
|
||||
ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
|
||||
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
|
||||
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
|
||||
#endif
|
||||
|
||||
|
|
@ -530,15 +583,15 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
|
|||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
u32 dcb_dhcsr = 0;
|
||||
int retval, timeout = 0;
|
||||
|
||||
/* Enter debug state on reset, cf. end_reset_event() */
|
||||
ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
|
||||
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
|
||||
|
||||
/* Request a reset */
|
||||
ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
|
||||
mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
|
||||
target->state = TARGET_RESET;
|
||||
|
||||
/* registers are now invalid */
|
||||
|
|
@ -546,10 +599,10 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
|
|||
|
||||
while (timeout < 100)
|
||||
{
|
||||
retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
|
||||
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
|
||||
if (retval == ERROR_OK)
|
||||
{
|
||||
ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
|
||||
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
|
||||
if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
|
||||
{
|
||||
LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
|
||||
|
|
@ -657,7 +710,7 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
|
|||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
breakpoint_t *breakpoint = NULL;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
|
|
@ -683,7 +736,7 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
|
|||
|
||||
/* set step and clear halt */
|
||||
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
|
||||
ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
|
||||
/* registers are now invalid */
|
||||
armv7m_invalidate_core_regs(target);
|
||||
|
|
@ -704,7 +757,7 @@ int cortex_m3_assert_reset(target_t *target)
|
|||
{
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
int assert_srst = 1;
|
||||
|
||||
LOG_DEBUG("target->state: %s",
|
||||
|
|
@ -717,17 +770,17 @@ int cortex_m3_assert_reset(target_t *target)
|
|||
}
|
||||
|
||||
/* Enable debug requests */
|
||||
ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
|
||||
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
|
||||
ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
|
||||
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
|
||||
|
||||
ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
|
||||
mem_ap_write_u32(swjdp, DCB_DCRDR, 0 );
|
||||
|
||||
if (!target->reset_halt)
|
||||
{
|
||||
/* Set/Clear C_MASKINTS in a separate operation */
|
||||
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
|
||||
ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
|
||||
mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
|
||||
|
||||
/* clear any debug flags before resuming */
|
||||
cortex_m3_clear_halt(target);
|
||||
|
|
@ -736,12 +789,12 @@ int cortex_m3_assert_reset(target_t *target)
|
|||
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
|
||||
|
||||
/* Enter debug state on reset, cf. end_reset_event() */
|
||||
ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
|
||||
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Enter debug state on reset, cf. end_reset_event() */
|
||||
ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
|
||||
mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
|
||||
}
|
||||
|
||||
/* following hack is to handle luminary reset
|
||||
|
|
@ -789,14 +842,14 @@ int cortex_m3_assert_reset(target_t *target)
|
|||
else
|
||||
{
|
||||
/* this causes the luminary device to reset using the watchdog */
|
||||
ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
|
||||
mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
|
||||
LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
|
||||
|
||||
{
|
||||
/* I do not know why this is necessary, but it fixes strange effects
|
||||
* (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
|
||||
u32 tmp;
|
||||
ahbap_read_system_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
|
||||
mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1179,13 +1232,12 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
|
|||
int retval;
|
||||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
|
||||
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
|
||||
{
|
||||
/* read a normal core register */
|
||||
retval = ahbap_read_coreregister_u32(swjdp, value, num);
|
||||
retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
|
||||
|
||||
if (retval != ERROR_OK)
|
||||
{
|
||||
|
|
@ -1197,7 +1249,7 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
|
|||
else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
|
||||
{
|
||||
/* read other registers */
|
||||
ahbap_read_coreregister_u32(swjdp, value, 20);
|
||||
cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
|
||||
|
||||
switch (num)
|
||||
{
|
||||
|
|
@ -1235,8 +1287,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
|
|||
|
||||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
|
||||
#ifdef ARMV7_GDB_HACKS
|
||||
/* If the LR register is being modified, make sure it will put us
|
||||
|
|
@ -1251,7 +1302,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
|
|||
|
||||
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
|
||||
{
|
||||
retval = ahbap_write_coreregister_u32(swjdp, value, num);
|
||||
retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
|
||||
if (retval != ERROR_OK)
|
||||
{
|
||||
LOG_ERROR("JTAG failure %i", retval);
|
||||
|
|
@ -1264,7 +1315,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
|
|||
{
|
||||
/* write other registers */
|
||||
|
||||
ahbap_read_coreregister_u32(swjdp, ®, 20);
|
||||
cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
|
||||
|
||||
switch (num)
|
||||
{
|
||||
|
|
@ -1285,7 +1336,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
|
|||
break;
|
||||
}
|
||||
|
||||
ahbap_write_coreregister_u32(swjdp, reg, 20);
|
||||
cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
|
||||
|
||||
LOG_DEBUG("write special reg %i value 0x%x ", num, value);
|
||||
}
|
||||
|
|
@ -1301,8 +1352,7 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co
|
|||
{
|
||||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
int retval;
|
||||
|
||||
/* sanitize arguments */
|
||||
|
|
@ -1314,13 +1364,13 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co
|
|||
switch (size)
|
||||
{
|
||||
case 4:
|
||||
retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address);
|
||||
retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
|
||||
break;
|
||||
case 2:
|
||||
retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
|
||||
retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
|
||||
break;
|
||||
case 1:
|
||||
retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
|
||||
retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("BUG: we shouldn't get here");
|
||||
|
|
@ -1334,8 +1384,7 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c
|
|||
{
|
||||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
int retval;
|
||||
|
||||
/* sanitize arguments */
|
||||
|
|
@ -1345,13 +1394,13 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c
|
|||
switch (size)
|
||||
{
|
||||
case 4:
|
||||
retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address);
|
||||
retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
|
||||
break;
|
||||
case 2:
|
||||
retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
|
||||
retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
|
||||
break;
|
||||
case 1:
|
||||
retval = ahbap_write_buf_u8(swjdp, buffer, count, address);
|
||||
retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("BUG: we shouldn't get here");
|
||||
|
|
@ -1386,7 +1435,7 @@ int cortex_m3_examine(struct target_s *target)
|
|||
/* get pointers to arch-specific information */
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
|
||||
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
|
||||
return retval;
|
||||
|
|
@ -1451,7 +1500,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
|
|||
{
|
||||
u16 dcrdr;
|
||||
|
||||
ahbap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
|
||||
mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
|
||||
*ctrl = (u8)dcrdr;
|
||||
*value = (u8)(dcrdr >> 8);
|
||||
|
||||
|
|
@ -1462,7 +1511,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
|
|||
if (dcrdr & (1 << 0))
|
||||
{
|
||||
dcrdr = 0;
|
||||
ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
|
||||
mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
|
|
@ -1471,8 +1520,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
|
|||
int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
|
||||
{
|
||||
armv7m_common_t *armv7m = target->arch_info;
|
||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
|
||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
|
||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
u8 data;
|
||||
u8 ctrl;
|
||||
u32 i;
|
||||
|
|
@ -1492,8 +1540,7 @@ int cortex_m3_handle_target_request(void *priv)
|
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if (!target->type->examined)
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||||
return ERROR_OK;
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||||
armv7m_common_t *armv7m = target->arch_info;
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||||
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
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||||
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
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||||
swjdp_common_t *swjdp = &armv7m->swjdp_info;
|
||||
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||||
if (!target->dbg_msg_enabled)
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||||
return ERROR_OK;
|
||||
|
|
@ -1534,10 +1581,10 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
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|||
cortex_m3->jtag_info.tap = tap;
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||||
cortex_m3->jtag_info.scann_size = 4;
|
||||
|
||||
cortex_m3->swjdp_info.dp_select_value = -1;
|
||||
cortex_m3->swjdp_info.ap_csw_value = -1;
|
||||
cortex_m3->swjdp_info.ap_tar_value = -1;
|
||||
cortex_m3->swjdp_info.jtag_info = &cortex_m3->jtag_info;
|
||||
armv7m->swjdp_info.dp_select_value = -1;
|
||||
armv7m->swjdp_info.ap_csw_value = -1;
|
||||
armv7m->swjdp_info.ap_tar_value = -1;
|
||||
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
|
||||
|
||||
/* initialize arch-specific breakpoint handling */
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@
|
|||
#include "register.h"
|
||||
#include "target.h"
|
||||
#include "armv7m.h"
|
||||
#include "cortex_swjdp.h"
|
||||
//#include "arm_adi_v5.h"
|
||||
|
||||
extern char* cortex_m3_state_strings[];
|
||||
|
||||
|
|
@ -162,7 +162,7 @@ typedef struct cortex_m3_common_s
|
|||
u32 *intsetenable;
|
||||
|
||||
armv7m_common_t armv7m;
|
||||
swjdp_common_t swjdp_info;
|
||||
// swjdp_common_t swjdp_info;
|
||||
void *arch_info;
|
||||
} cortex_m3_common_t;
|
||||
|
||||
|
|
@ -188,7 +188,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
|
|||
int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
|
||||
int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
|
||||
|
||||
extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
|
||||
//extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
|
||||
extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
|
||||
|
||||
#endif /* CORTEX_M3_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue