ARM: use arm_reg_current()
Start using the arm_reg_current() call. This shrinks and speeds the affected code. It can also prevent some coredumps coming from invalid CPSR values ... the ARMV4_5_CORE_REG_MODE() macro returns bogus registers if e.g. "Secure Monitor" mode isn't supported by the current CPU. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
fa618cc74d
commit
b404b9ab57
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@ -1245,9 +1245,11 @@ int arm7_9_soft_reset_halt(struct target *target)
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/* reset registers */
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for (i = 0; i <= 14; i++)
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{
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
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struct reg *r = arm_reg_current(armv4_5, i);
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buf_set_u32(r->value, 0, 32, 0xffffffff);
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r->dirty = 1;
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r->valid = 1;
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}
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if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
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@ -1443,32 +1445,31 @@ static int arm7_9_debug_entry(struct target *target)
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for (i = 0; i <= 15; i++)
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{
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struct reg *r = arm_reg_current(armv4_5, i);
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LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
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buf_set_u32(r->value, 0, 32, context[i]);
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/* r0 and r15 (pc) have to be restored later */
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r->dirty = (i == 0) || (i == 15);
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r->valid = 1;
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}
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LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
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/* exceptions other than USR & SYS have a saved program status register */
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if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
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{
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if (armv4_5->spsr) {
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uint32_t spsr;
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arm7_9->read_xpsr(target, &spsr, 1);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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return retval;
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}
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
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buf_set_u32(armv4_5->spsr->value, 0, 32, spsr);
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armv4_5->spsr->dirty = 0;
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armv4_5->spsr->valid = 1;
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}
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/* r0 and r15 (pc) have to be restored later */
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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return retval;
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@ -2377,8 +2378,11 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
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if (!is_arm_mode(armv4_5->core_mode))
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return ERROR_FAIL;
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for (i = 0; i <= last_reg; i++)
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
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for (i = 0; i <= last_reg; i++) {
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struct reg *r = arm_reg_current(armv4_5, i);
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r->dirty = r->valid;
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}
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arm7_9->read_xpsr(target, &cpsr, 0);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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@ -2562,8 +2566,11 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
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if (!is_arm_mode(armv4_5->core_mode))
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return ERROR_FAIL;
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for (i = 0; i <= last_reg; i++)
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
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for (i = 0; i <= last_reg; i++) {
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struct reg *r = arm_reg_current(armv4_5, i);
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r->dirty = r->valid;
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}
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arm7_9->read_xpsr(target, &cpsr, 0);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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@ -216,6 +216,7 @@ static int arm920t_read_cp15_interpreted(struct target *target,
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uint32_t* regs_p[1];
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uint32_t regs[2];
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uint32_t cp15c15 = 0x0;
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struct reg *r = armv4_5->core_cache->reg_list;
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/* load address into R1 */
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regs[1] = address;
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@ -247,8 +248,8 @@ static int arm920t_read_cp15_interpreted(struct target *target,
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if (!is_arm_mode(armv4_5->core_mode))
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return ERROR_FAIL;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
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r[0].dirty = 1;
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r[1].dirty = 1;
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return ERROR_OK;
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}
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@ -260,6 +261,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
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uint32_t cp15c15 = 0x0;
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struct arm *armv4_5 = target_to_armv4_5(target);
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uint32_t regs[2];
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struct reg *r = armv4_5->core_cache->reg_list;
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/* load value, address into R0, R1 */
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regs[0] = value;
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@ -287,8 +289,8 @@ int arm920t_write_cp15_interpreted(struct target *target,
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if (!is_arm_mode(armv4_5->core_mode))
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return ERROR_FAIL;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
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r[0].dirty = 1;
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r[1].dirty = 1;
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return ERROR_OK;
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}
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@ -678,6 +680,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
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FILE *output;
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struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
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int segment, index;
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struct reg *r;
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retval = arm920t_verify_pointer(CMD_CTX, arm920t);
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if (retval != ERROR_OK)
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@ -893,17 +896,22 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
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if (!is_arm_mode(armv4_5->core_mode))
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return ERROR_FAIL;
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/* mark registers dirty. */
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
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/* force writeback of the valid data */
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r = armv4_5->core_cache->reg_list;
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r[0].dirty = r[0].valid;
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r[1].dirty = r[1].valid;
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r[2].dirty = r[2].valid;
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r[3].dirty = r[3].valid;
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r[4].dirty = r[4].valid;
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r[5].dirty = r[5].valid;
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r[6].dirty = r[6].valid;
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r[7].dirty = r[7].valid;
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r = arm_reg_current(armv4_5, 8);
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r->dirty = r->valid;
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r = arm_reg_current(armv4_5, 9);
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r->dirty = r->valid;
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return ERROR_OK;
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}
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@ -924,6 +932,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
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uint32_t Dlockdown, Ilockdown;
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struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
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int victim;
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struct reg *r;
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retval = arm920t_verify_pointer(CMD_CTX, arm920t);
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if (retval != ERROR_OK)
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@ -1176,17 +1185,22 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
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if (!is_arm_mode(armv4_5->core_mode))
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return ERROR_FAIL;
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/* mark registers dirty */
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
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/* force writeback of the valid data */
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r = armv4_5->core_cache->reg_list;
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r[0].dirty = r[0].valid;
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r[1].dirty = r[1].valid;
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r[2].dirty = r[2].valid;
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r[3].dirty = r[3].valid;
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r[4].dirty = r[4].valid;
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r[5].dirty = r[5].valid;
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r[6].dirty = r[6].valid;
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r[7].dirty = r[7].valid;
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r = arm_reg_current(armv4_5, 8);
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r->dirty = r->valid;
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r = arm_reg_current(armv4_5, 9);
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r->dirty = r->valid;
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return ERROR_OK;
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}
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@ -496,8 +496,7 @@ static int cortex_a8_resume(struct target *target, int current,
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/* current = 1: continue on current pc, otherwise continue at <address> */
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resume_pc = buf_get_u32(
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).value,
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armv4_5->core_cache->reg_list[15].value,
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0, 32);
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if (!current)
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resume_pc = address;
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@ -522,13 +521,10 @@ static int cortex_a8_resume(struct target *target, int current,
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return ERROR_FAIL;
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}
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LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).value,
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buf_set_u32(armv4_5->core_cache->reg_list[15].value,
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0, 32, resume_pc);
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).dirty = 1;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).valid = 1;
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armv4_5->core_cache->reg_list[15].dirty = 1;
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armv4_5->core_cache->reg_list[15].valid = 1;
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cortex_a8_restore_context(target);
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@ -653,8 +649,7 @@ static int cortex_a8_debug_entry(struct target *target)
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/* update cache */
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for (i = 0; i <= ARM_PC; i++)
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{
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reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, i);
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reg = arm_reg_current(armv4_5, i);
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buf_set_u32(reg->value, 0, 32, regfile[i]);
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reg->valid = 1;
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@ -672,13 +667,10 @@ static int cortex_a8_debug_entry(struct target *target)
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// ARM state
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regfile[ARM_PC] -= 8;
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}
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, ARM_PC).value,
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0, 32, regfile[ARM_PC]);
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
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.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 0).valid;
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reg = armv4_5->core_cache->reg_list + 15;
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buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
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reg->dirty = reg->valid;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
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.dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
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armv4_5->core_mode, 15).valid;
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