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cortex_a: remove cache handlers from cortex_a_write_phys_memory 

This was needed for ahb access

Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/2796
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This commit is contained in:
Oleksij Rempel 2015-05-15 09:03:54 +02:00 committed by Paul Fertser
parent f478107d02
commit b55361d07f
1 changed files with 0 additions and 54 deletions
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54
src/target/cortex_a.c
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@ -2698,60 +2698,6 @@ static int cortex_a_write_phys_memory(struct target *target,
return cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
}
/* REVISIT this op is generic ARMv7-A/R stuff */
if (retval == ERROR_OK && target->state == TARGET_HALTED) {
struct arm_dpm *dpm = armv7a->arm.dpm;
retval = dpm->prepare(dpm);
if (retval != ERROR_OK)
return retval;
/* The Cache handling will NOT work with MMU active, the
* wrong addresses will be invalidated!
*
* For both ICache and DCache, walk all cache lines in the
* address range. Cortex-A has fixed 64 byte line length.
*
* REVISIT per ARMv7, these may trigger watchpoints ...
*/
/* invalidate I-Cache */
if (armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled) {
/* ICIMVAU - Invalidate Cache single entry
* with MVA to PoU
* MCR p15, 0, r0, c7, c5, 1
*/
for (uint32_t cacheline = 0;
cacheline < size * count;
cacheline += 64) {
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
address + cacheline);
if (retval != ERROR_OK)
return retval;
}
}
/* invalidate D-Cache */
if (armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled) {
/* DCIMVAC - Invalidate data Cache line
* with MVA to PoC
* MCR p15, 0, r0, c7, c6, 1
*/
for (uint32_t cacheline = 0;
cacheline < size * count;
cacheline += 64) {
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
address + cacheline);
if (retval != ERROR_OK)
return retval;
}
}
/* (void) */ dpm->finish(dpm);
}
return retval;
}