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sim3x: new flash driver for Silabs SiM3 microcontroller family 

This is a new driver for Silicon Laboratories SiM3 microcontroller
family, based on the work of Ladislav Bábel. The driver will try to
detect the type of MCU from the device id register, and if this
fails it will use the flash size from the flash bank command.
Driver added to the documentation and to the README.
TCL script added.

Tests:
* Hardware: SiM3C166 (pre-production) and SiM3U167
* Binary: 4kb, 197kb, 256kb
* Flash protect not tested

Change-Id: I701e0cf505ca8ad99be7f83543fe5055b2f65dcc
Signed-off-by: Andreas Bomholtz <andreas@seluxit.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2078
Tested-by: jenkins
This commit is contained in:
Andreas Bomholtz 2015-01-08 14:08:26 +01:00 committed by Andreas Fritiofson
parent 233f8859c0
commit bdbe78f131
7 changed files with 1349 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
README
View File

@ -127,9 +127,10 @@ Flash drivers
-------------
ADUC702x, AT91SAM, AVR, CFI, DSP5680xx, EFM32, EM357, FM3, Kinetis,
LPC2000, LPC2900, LPCSPIFI, Milandr, NuMicro, PIC32mx, PSoC4, Stellaris,
STM32, STMSMI, STR7x, STR9x, nRF51; NAND controllers of AT91SAM9, LPC3180,
LPC32xx, i.MX31, MXC, NUC910, Orion/Kirkwood, S3C24xx, S3C6400.
LPC2000, LPC2900, LPCSPIFI, Milandr, NuMicro, PIC32mx, PSoC4, SiM3x,
Stellaris, STM32, STMSMI, STR7x, STR9x, nRF51; NAND controllers of
AT91SAM9, LPC3180, LPC32xx, i.MX31, MXC, NUC910, Orion/Kirkwood,
S3C24xx, S3C6400.
==================

81
contrib/loaders/flash/sim3x.s Normal file
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@ -0,0 +1,81 @@
/***************************************************************************
* Copyright (C) 2014 by Ladislav Bábel *
* ladababel@seznam.cz *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
***************************************************************************/
#define INITIAL_UNLOCK 0x5A
#define MULTIPLE_UNLOCK 0xF2
#define FLASHCTRL_KEY 0x4002E0C0
#define FLASHCTRL_CONFIG 0x4002E000
#define FLASHCTRL_WRADDR 0x4002E0A0
#define FLASHCTRL_WRDATA 0x4002E0B0
#define BUSYF 0x00100000
/* Write the initial unlock value to KEY (0xA5) */
movs r6, #INITIAL_UNLOCK
str r6, [r0, #FLASHCTRL_KEY]
/* Write the multiple unlock value to KEY (0xF2) */
movs r6, #MULTIPLE_UNLOCK
str r6, [r0, #FLASHCTRL_KEY]
wait_fifo:
ldr r6, [r2, #0]
cmp r6, #0
beq exit
ldr r5, [r2, #4]
cmp r5, r6
beq wait_fifo
/* wait for BUSYF flag */
wait_busy1:
ldr r6, [r0, #FLASHCTRL_CONFIG]
tst r6, #BUSYF
bne wait_busy1
/* Write the destination address to WRADDR */
str r4, [r0, #FLASHCTRL_WRADDR]
/* Write the data half-word to WRDATA in right-justified format */
ldrh r6, [r5]
str r6, [r0, #FLASHCTRL_WRDATA]
adds r5, #2
adds r4, #2
/* wrap rp at end of buffer */
cmp r5, r3
bcc no_wrap
mov r5, r2
adds r5, #8
no_wrap:
str r5, [r2, #4]
subs r1, r1, #1
cmp r1, #0
beq exit
b wait_fifo
exit:
movs r6, #MULTIPLE_LOCK
str r6, [r0, #FLASHCTRL_KEY]
/* wait for BUSYF flag */
wait_busy2:
ldr r6, [r0, #FLASHCTRL_CONFIG]
tst r6, #BUSYF
bne wait_busy2
bkpt #0

111
doc/openocd.texi
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@ -1447,49 +1447,49 @@ When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
the target config file defines all of them.
@example
$ ls target
aduc702x.cfg lpc1763.cfg
am335x.cfg lpc1764.cfg
amdm37x.cfg lpc1765.cfg
ar71xx.cfg lpc1766.cfg
at32ap7000.cfg lpc1767.cfg
at91r40008.cfg lpc1768.cfg
at91rm9200.cfg lpc1769.cfg
at91sam3ax_4x.cfg lpc1788.cfg
at91sam3ax_8x.cfg lpc17xx.cfg
at91sam3ax_xx.cfg lpc1850.cfg
at91sam3nXX.cfg lpc2103.cfg
at91sam3sXX.cfg lpc2124.cfg
at91sam3u1c.cfg lpc2129.cfg
at91sam3u1e.cfg lpc2148.cfg
at91sam3u2c.cfg lpc2294.cfg
at91sam3u2e.cfg lpc2378.cfg
at91sam3u4c.cfg lpc2460.cfg
at91sam3u4e.cfg lpc2478.cfg
at91sam3uxx.cfg lpc2900.cfg
at91sam3XXX.cfg lpc2xxx.cfg
at91sam4sd32x.cfg lpc3131.cfg
at91sam4sXX.cfg lpc3250.cfg
at91sam4XXX.cfg lpc4350.cfg
at91sam7se512.cfg lpc4350.cfg.orig
at91sam7sx.cfg mc13224v.cfg
at91sam7x256.cfg nuc910.cfg
at91sam7x512.cfg omap2420.cfg
at91sam9260.cfg omap3530.cfg
at91sam9260_ext_RAM_ext_flash.cfg omap4430.cfg
at91sam9261.cfg omap4460.cfg
at91sam9263.cfg omap5912.cfg
at91sam9.cfg omapl138.cfg
at91sam9g10.cfg pic32mx.cfg
at91sam9g20.cfg pxa255.cfg
at91sam9g45.cfg pxa270.cfg
at91sam9rl.cfg pxa3xx.cfg
atmega128.cfg readme.txt
avr32.cfg samsung_s3c2410.cfg
c100.cfg samsung_s3c2440.cfg
c100config.tcl samsung_s3c2450.cfg
c100helper.tcl samsung_s3c4510.cfg
c100regs.tcl samsung_s3c6410.cfg
cs351x.cfg sharp_lh79532.cfg
aduc702x.cfg lpc1764.cfg
am335x.cfg lpc1765.cfg
amdm37x.cfg lpc1766.cfg
ar71xx.cfg lpc1767.cfg
at32ap7000.cfg lpc1768.cfg
at91r40008.cfg lpc1769.cfg
at91rm9200.cfg lpc1788.cfg
at91sam3ax_4x.cfg lpc17xx.cfg
at91sam3ax_8x.cfg lpc1850.cfg
at91sam3ax_xx.cfg lpc2103.cfg
at91sam3nXX.cfg lpc2124.cfg
at91sam3sXX.cfg lpc2129.cfg
at91sam3u1c.cfg lpc2148.cfg
at91sam3u1e.cfg lpc2294.cfg
at91sam3u2c.cfg lpc2378.cfg
at91sam3u2e.cfg lpc2460.cfg
at91sam3u4c.cfg lpc2478.cfg
at91sam3u4e.cfg lpc2900.cfg
at91sam3uxx.cfg lpc2xxx.cfg
at91sam3XXX.cfg lpc3131.cfg
at91sam4sd32x.cfg lpc3250.cfg
at91sam4sXX.cfg lpc4350.cfg
at91sam4XXX.cfg lpc4350.cfg.orig
at91sam7se512.cfg mc13224v.cfg
at91sam7sx.cfg nuc910.cfg
at91sam7x256.cfg omap2420.cfg
at91sam7x512.cfg omap3530.cfg
at91sam9260.cfg omap4430.cfg
at91sam9260_ext_RAM_ext_flash.cfg omap4460.cfg
at91sam9261.cfg omap5912.cfg
at91sam9263.cfg omapl138.cfg
at91sam9.cfg pic32mx.cfg
at91sam9g10.cfg pxa255.cfg
at91sam9g20.cfg pxa270.cfg
at91sam9g45.cfg pxa3xx.cfg
at91sam9rl.cfg readme.txt
atmega128.cfg samsung_s3c2410.cfg
avr32.cfg samsung_s3c2440.cfg
c100.cfg samsung_s3c2450.cfg
c100config.tcl samsung_s3c4510.cfg
c100helper.tcl samsung_s3c6410.cfg
c100regs.tcl sharp_lh79532.cfg
cs351x.cfg sim3x.cfg
davinci.cfg smp8634.cfg
dragonite.cfg spear3xx.cfg
dsp56321.cfg stellaris.cfg
@ -1524,6 +1524,7 @@ lpc1754.cfg ti_dm6446.cfg
lpc1756.cfg tmpa900.cfg
lpc1758.cfg tmpa910.cfg
lpc1759.cfg u8500.cfg
lpc1763.cfg
@end example
@item @emph{more} ... browse for other library files which may be useful.
For example, there are various generic and CPU-specific utilities.
@ -5720,6 +5721,30 @@ flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
@end example
@end deffn
@deffn {Flash Driver} sim3x
All members of the SiM3 microcontroller family from Silicon Laboratories
include internal flash and use ARM Cortex M3 cores. It supports both JTAG
and SWD interface.
The @var{sim3x} driver tries to probe the device to auto detect the MCU.
If this failes, it will use the @var{size} parameter as the size of flash bank.
@example
flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
@end example
There are 2 commands defined in the @var{sim3x} driver:
@deffn Command {sim3x mass_erase}
Erases the complete flash. This is used to unlock the flash.
And this command is only possible when using the SWD interface.
@end deffn
@deffn Command {sim3x lock}
Lock the flash. To unlock use the @command{sim3x mass_erase} command.
@end deffn
@end deffn
@subsection str9xpec driver
@cindex str9xpec

3
src/flash/nor/Makefile.am
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@ -45,7 +45,8 @@ NOR_DRIVERS = \
nuc1x.c \
nrf51.c \
mrvlqspi.c \
psoc4.c
psoc4.c \
sim3x.c
noinst_HEADERS = \
core.h \

2
src/flash/nor/drivers.c
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@ -58,6 +58,7 @@ extern struct flash_driver nuc1x_flash;
extern struct flash_driver nrf51_flash;
extern struct flash_driver mrvlqspi_flash;
extern struct flash_driver psoc4_flash;
extern struct flash_driver sim3x_flash;
/**
* The list of built-in flash drivers.
@ -100,6 +101,7 @@ static struct flash_driver *flash_drivers[] = {
&nrf51_flash,
&mrvlqspi_flash,
&psoc4_flash,
&sim3x_flash,
NULL,
};

1137
src/flash/nor/sim3x.c Normal file
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File diff suppressed because it is too large Load Diff

55
tcl/target/sim3x.cfg Executable file
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@ -0,0 +1,55 @@
#
# Silicon Laboratories SiM3x Cortex-M3
#
# SiM3x devices support both JTAG and SWD transports.
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME SiM3x
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4ba00477
}
if { [info exists CPURAMSIZE] } {
set _CPURAMSIZE $CPURAMSIZE
} else {
# Minimum size of RAM in the Silicon Labs product matrix (8KB)
set _CPURAMSIZE 0x2000
}
if { [info exists CPUROMSIZE] } {
set _CPUROMSIZE $CPUROMSIZE
} else {
# Minimum size of FLASH in the Silicon Labs product matrix (32KB)
set _CPUROMSIZE 0x8000
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE $_CPURAMSIZE
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
adapter_khz 1000
adapter_nsrst_delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}