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aarch64: run control rework

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This patch contains a major overhaul of the target run control,
mainly for the sake of satisfying gdbs ideas of how a target
should respond to various control requests for the debugger.

The changes allow gdb a slightly better control on how cores
are stepped: a core can be single-stepped while 
other cores remain halted or continue normal execution 
until the single-stepped core halts again.

Also, on any halting event (user command or breakpoint) the
system is brought into a stable state with all cores halted
before the halt is signaled to the debugger.

This patch also transitions the target code to make use of the
new CTI abstraction instead of accessing CTI registers directly.

Change-Id: I8ddc9abb119e04580d671b57ee12240c3f5070a0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3993
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Matthias Welwarsky 2017-02-17 14:24:53 +01:00 committed by Paul Fertser
parent e513fe949b
commit bf1efe05bb
3 changed files with 619 additions and 300 deletions
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874
src/target/aarch64.c
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File diff suppressed because it is too large Load Diff

38
src/target/armv8.h
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@ -24,6 +24,7 @@
#include "armv4_5_mmu.h"
#include "armv4_5_cache.h"
#include "armv8_dpm.h"
#include "arm_cti.h"
enum {
ARMV8_R0 = 0,
@ -155,7 +156,6 @@ struct armv8_common {
/* Core Debug Unit */
struct arm_dpm dpm;
uint32_t debug_base;
uint32_t cti_base;
struct adiv5_ap *debug_ap;
const uint32_t *opcodes;
@ -173,6 +173,8 @@ struct armv8_common {
struct armv8_mmu_common armv8_mmu;
struct arm_cti *cti;
/* Direct processor core register read and writes */
int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
@ -222,40 +224,6 @@ target_to_armv8(struct target *target)
#define CPUV8_DBG_AUTHSTATUS 0xFB8
/*define CTI(cross trigger interface)*/
#define CTI_CTR 0x0
#define CTI_INACK 0x10
#define CTI_APPSET 0x14
#define CTI_APPCLEAR 0x18
#define CTI_APPPULSE 0x1C
#define CTI_INEN0 0x20
#define CTI_INEN1 0x24
#define CTI_INEN2 0x28
#define CTI_INEN3 0x2C
#define CTI_INEN4 0x30
#define CTI_INEN5 0x34
#define CTI_INEN6 0x38
#define CTI_INEN7 0x3C
#define CTI_OUTEN0 0xA0
#define CTI_OUTEN1 0xA4
#define CTI_OUTEN2 0xA8
#define CTI_OUTEN3 0xAC
#define CTI_OUTEN4 0xB0
#define CTI_OUTEN5 0xB4
#define CTI_OUTEN6 0xB8
#define CTI_OUTEN7 0xBC
#define CTI_TRIN_STATUS 0x130
#define CTI_TROUT_STATUS 0x134
#define CTI_CHIN_STATUS 0x138
#define CTI_CHOU_STATUS 0x13C
#define CTI_GATE 0x140
#define CTI_UNLOCK 0xFB0
#define CTI_CHNL(x) (1 << x)
#define CTI_TRIG_HALT 0
#define CTI_TRIG_RESUME 1
#define CTI_TRIG(n) (1 << CTI_TRIG_##n)
#define PAGE_SIZE_4KB 0x1000
#define PAGE_SIZE_4KB_LEVEL0_BITS 39
#define PAGE_SIZE_4KB_LEVEL1_BITS 30

7
src/target/armv8_dpm.h
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@ -96,7 +96,7 @@ void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
#define DRCR_RESTART (1 << 1)
#define DRCR_CLEAR_EXCEPTIONS (1 << 2)
/* PRCR (processor debug status register) bits */
/* PRSR (processor debug status register) bits */
#define PRSR_PU (1 << 0)
#define PRSR_SPD (1 << 1)
#define PRSR_RESET (1 << 2)
@ -110,6 +110,11 @@ void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
#define PRSR_SPMAD (1 << 10)
#define PRSR_SDR (1 << 11)
/* PRCR (processor debug control register) bits */
#define PRCR_CORENPDRQ (1 << 0)
#define PRCR_CWRR (1 << 2)
#define PRCR_COREPURQ (1 << 3)
void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
void armv8_dpm_handle_exception(struct arm_dpm *dpm);
enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm);