Cortex-A8: implement DPM
This implements the DPM interface for Cortex-A8 cores. It also adds a synchronization operation to the DPM framework, which is needed by the Cortex-A8 after CPSR writes. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
991daa03eb
commit
c008d30fe8
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@ -52,10 +52,8 @@ static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
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retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
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/* REVISIT on Cortex-A8, we need a Prefetch Flush operation too ...
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cortex_a8_exec_opcode(target,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
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*/
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if (dpm->instr_cpsr_sync)
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retval = dpm->instr_cpsr_sync(dpm);
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return retval;
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}
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@ -142,11 +140,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
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value);
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/* REVISIT on Cortex-A8, we need a Prefetch Flush operation
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* after writing CPSR ...
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cortex_a8_exec_opcode(target,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
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*/
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if (regnum == 16 && dpm->instr_cpsr_sync)
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retval = dpm->instr_cpsr_sync(dpm);
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break;
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}
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@ -61,6 +61,9 @@ struct arm_dpm {
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int (*instr_write_data_r0)(struct arm_dpm *,
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uint32_t opcode, uint32_t data);
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/** Optional core-specific operation invoked after CPSR writes. */
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int (*instr_cpsr_sync)(struct arm_dpm *dpm);
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/* READ FROM CPU */
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/** Runs one instruction, reading data from dcc after execution. */
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@ -23,6 +23,7 @@
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#include "armv4_5.h"
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#include "armv4_5_mmu.h"
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#include "armv4_5_cache.h"
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#include "arm_dpm.h"
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enum
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{
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@ -53,6 +54,7 @@ struct armv7a_common
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struct swjdp_common swjdp_info;
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/* Core Debug Unit */
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struct arm_dpm dpm;
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uint32_t debug_base;
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uint8_t debug_ap;
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uint8_t memory_ap;
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@ -351,6 +351,173 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_
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return retval;
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}
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/*
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* Cortex-A8 implementation of Debug Programmer's Model
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*
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* NOTE that in several of these cases the "stall" mode might be useful.
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* It'd let us queue a few operations together... prepare/finish might
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* be the places to enable/disable that mode.
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*/
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static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
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{
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return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
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}
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static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
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{
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LOG_DEBUG("write DCC 0x%08" PRIx32, data);
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return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
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a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
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}
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static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data)
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{
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struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
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uint32_t dscr;
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int retval;
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/* Wait for DTRRXfull */
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do {
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retval = mem_ap_read_atomic_u32(swjdp,
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a8->armv7a_common.debug_base + CPUDBG_DSCR,
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&dscr);
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} while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0);
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retval = mem_ap_read_atomic_u32(swjdp,
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a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
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LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
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return retval;
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}
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static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
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{
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struct cortex_a8_common *a8 = dpm_to_a8(dpm);
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struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
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uint32_t dscr;
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int retval;
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retval = mem_ap_read_atomic_u32(swjdp,
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a8->armv7a_common.debug_base + CPUDBG_DSCR,
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&dscr);
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/* this "should never happen" ... */
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if (dscr & (1 << DSCR_DTR_RX_FULL)) {
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LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
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/* Clear DCCRX */
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retval = cortex_a8_exec_opcode(
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a8->armv7a_common.armv4_5_common.target,
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ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
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}
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return retval;
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}
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static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
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{
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/* REVISIT what could be done here? */
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return ERROR_OK;
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}
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static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t data)
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{
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struct cortex_a8_common *a8 = dpm_to_a8(dpm);
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int retval;
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retval = cortex_a8_write_dcc(a8, data);
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return cortex_a8_exec_opcode(
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a8->armv7a_common.armv4_5_common.target,
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opcode);
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}
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static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t data)
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{
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struct cortex_a8_common *a8 = dpm_to_a8(dpm);
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int retval;
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retval = cortex_a8_write_dcc(a8, data);
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/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
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retval = cortex_a8_exec_opcode(
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a8->armv7a_common.armv4_5_common.target,
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ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
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/* then the opcode, taking data from R0 */
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retval = cortex_a8_exec_opcode(
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a8->armv7a_common.armv4_5_common.target,
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opcode);
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return retval;
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}
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static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
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{
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struct target *target = dpm->arm->target;
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/* "Prefetch flush" after modifying execution status in CPSR */
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return cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
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}
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static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t *data)
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{
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struct cortex_a8_common *a8 = dpm_to_a8(dpm);
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int retval;
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/* the opcode, writing data to DCC */
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retval = cortex_a8_exec_opcode(
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a8->armv7a_common.armv4_5_common.target,
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opcode);
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return cortex_a8_read_dcc(a8, data);
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}
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static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t *data)
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{
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struct cortex_a8_common *a8 = dpm_to_a8(dpm);
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int retval;
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/* the opcode, writing data to R0 */
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retval = cortex_a8_exec_opcode(
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a8->armv7a_common.armv4_5_common.target,
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opcode);
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/* write R0 to DCC */
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retval = cortex_a8_exec_opcode(
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a8->armv7a_common.armv4_5_common.target,
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ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
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return cortex_a8_read_dcc(a8, data);
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}
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// static
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int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
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{
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struct arm_dpm *dpm = &a8->armv7a_common.dpm;
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dpm->arm = &a8->armv7a_common.armv4_5_common;
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dpm->didr = didr;
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dpm->prepare = cortex_a8_dpm_prepare;
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dpm->finish = cortex_a8_dpm_finish;
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dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
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dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
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dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
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dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
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dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
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return arm_dpm_setup(dpm);
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}
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/*
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* Cortex-A8 Run control
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*/
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