ARM11: remove old mrc/mcr commands
Switch to new commands in config scripts Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Øyvind Harboe
parent
1f357869c1
commit
c202ba7d34
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@ -1502,7 +1502,7 @@ proc setc15 @{regs value@} @{
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echo [format "set p15 0x%04x, 0x%08x" $regs $value]
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arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
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mcr 15 [expr ($regs>>12)&0x7] \
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[expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
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[expr ($regs>>8)&0x7] $value
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@}
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@ -5796,15 +5796,6 @@ Without arguments, the current settings are displayed.
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@subsection ARM11 specific commands
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@cindex ARM11
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@deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
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Write @var{value} to a coprocessor @var{pX} register
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passing parameters @var{CRn},
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@var{CRm}, opcodes @var{opc1} and @var{opc2},
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and the MCR instruction.
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(The difference beween this and the MCR2 instruction is
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one bit in the encoding, effecively a fifth parameter.)
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@end deffn
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@deffn Command {arm11 memwrite burst} [value]
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Displays the value of the memwrite burst-enable flag,
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which is enabled by default. Burst writes are only used
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@ -5821,15 +5812,6 @@ which is enabled by default.
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If @var{value} is defined, first assigns that.
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@end deffn
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@deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
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Read a coprocessor @var{pX} register passing parameters @var{CRn},
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@var{CRm}, opcodes @var{opc1} and @var{opc2},
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and the MRC instruction.
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(The difference beween this and the MRC2 instruction is
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one bit in the encoding, effecively a fifth parameter.)
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Displays the result.
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@end deffn
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@deffn Command {arm11 step_irq_enable} [value]
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Displays the value of the flag controlling whether
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IRQs are enabled during single stepping;
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@ -2087,101 +2087,6 @@ static arm11_common_t * arm11_find_target(const char * arg)
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return 0;
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}
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static int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc, bool read)
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{
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int retval;
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if (argc != (read ? 6 : 7))
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{
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LOG_ERROR("Invalid number of arguments.");
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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arm11_common_t * arm11 = arm11_find_target(args[0]);
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if (!arm11)
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{
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LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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if (arm11->target->state != TARGET_HALTED)
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{
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LOG_WARNING("target was not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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uint32_t values[6];
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for (size_t i = 0; i < (read ? 5 : 6); i++)
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{
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COMMAND_PARSE_NUMBER(u32, args[i + 1], values[i]);
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if (values[i] > arm11_coproc_instruction_limits[i])
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{
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LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
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(long)(i + 2),
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arm11_coproc_instruction_limits[i]);
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return ERROR_COMMAND_SYNTAX_ERROR;
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}
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}
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uint32_t instr = 0xEE000010 |
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(values[0] << 8) |
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(values[1] << 21) |
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(values[2] << 16) |
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(values[3] << 0) |
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(values[4] << 5);
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if (read)
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instr |= 0x00100000;
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retval = arm11_run_instr_data_prepare(arm11);
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if (retval != ERROR_OK)
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return retval;
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if (read)
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{
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uint32_t result;
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retval = arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
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if (retval != ERROR_OK)
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return retval;
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LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
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(int)(values[0]),
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(int)(values[1]),
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(int)(values[2]),
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(int)(values[3]),
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(int)(values[4]), result, result);
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}
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else
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{
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retval = arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
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if (retval != ERROR_OK)
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return retval;
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LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
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(int)(values[0]), (int)(values[1]),
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values[5],
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(int)(values[2]), (int)(values[3]), (int)(values[4]));
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}
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return arm11_run_instr_data_finish(arm11);
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}
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static int arm11_handle_mrc(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, true);
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}
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static int arm11_handle_mcr(struct command_context_s *cmd_ctx,
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char *cmd, char **args, int argc)
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{
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return arm11_handle_mrc_mcr(cmd_ctx, cmd, args, argc, false);
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}
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static int arm11_mrc_inner(target_t *target, int cpnum,
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uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
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uint32_t *value, bool read)
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@ -2300,10 +2205,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
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"DEBUG ONLY - Hardware single stepping"
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" (default: disabled)");
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register_command(cmd_ctx, top_cmd, "mcr",
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arm11_handle_mcr, COMMAND_ANY,
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"Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
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mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
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NULL, COMMAND_ANY, NULL);
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register_command(cmd_ctx, mw_cmd, "burst",
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@ -2315,9 +2216,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
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"Terminate program if transfer error was found"
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" (default: enabled)");
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register_command(cmd_ctx, top_cmd, "mrc",
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arm11_handle_mrc, COMMAND_ANY,
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"Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
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register_command(cmd_ctx, top_cmd, "step_irq_enable",
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arm11_handle_bool_step_irq_enable, COMMAND_ANY,
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"Enable interrupts while stepping"
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@ -19,13 +19,13 @@ proc csb732_init { } {
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# We assume the interpreter latency is enough.
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# Allow access to all coprocessors
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arm11 mcr imx35.cpu 15 0 15 1 0 0x2001
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mcr 15 0 15 1 0 0x2001
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# Disable MMU, caches, write buffer
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arm11 mcr imx35.cpu 15 0 1 0 0 0x78
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mcr 15 0 1 0 0 0x78
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# Grant manager access to all domains
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arm11 mcr imx35.cpu 15 0 3 0 0 0xFFFFFFFF
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mcr 15 0 3 0 0 0xFFFFFFFF
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# Set ARM clock to 532 MHz, AHB to 133 MHz
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mww 0x53F80004 0x1000
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@ -436,22 +436,22 @@ proc initC100 {} {
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# */
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# mov r0, #0
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# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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arm11 mcr c100.cpu 15 0 7 7 0 0x0
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mcr 15 0 7 7 0 0x0
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# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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arm11 mcr c100.cpu 15 0 8 7 0 0x0
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mcr 15 0 8 7 0 0x0
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# /*
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# * disable MMU stuff and caches
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# */
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# mrc p15, 0, r0, c1, c0, 0
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arm11 mrc c100.cpu 15 0 1 0 0
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mrc 15 0 1 0 0
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# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
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# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
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# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
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# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
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# orr r0, r0, #0x00400000 @ set bit 22 (U)
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# mcr p15, 0, r0, c1, c0, 0
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arm11 mcr c100.cpu 15 0 1 0 0 0x401002
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mcr 15 0 1 0 0 0x401002
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# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
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# APB init
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# // Setting APB Bus Wait states to 1, set post write
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@ -10,7 +10,7 @@ proc setc15 {regs value} {
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echo [format "set p15 0x%04x, 0x%08x" $regs $value]
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arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
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mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
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}
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