arm_adi_v5: rework dap_read_part_id()
Rework dap_read_part_id() while preparing for reorganizing the 'ROM Table Parsing' (RTP): - rename it with 'rtp' prefix; - extends it to read other CoreSight registers, thus improving the overall speed by queuing more reads; - reduce the list of arguments by using a struct; - reorder the reads by increasing offset, potentially gaining speed using MEM_AP_REG_BDx and/or auto-increment; - log a debug message in case of read error. Change-Id: I6544ac7740b808a6c0fbacf97ac00b97f5bd3832 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6815 Tested-by: jenkins
This commit is contained in:
Antonio Borneo
parent
1fd2a6c7f5
commit
c3f6e21d5c
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@ -1094,53 +1094,80 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
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return ERROR_OK;
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}
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static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, uint32_t *cid, uint64_t *pid)
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/** Holds registers of a CoreSight component */
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struct cs_component_vals {
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uint64_t pid;
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uint32_t cid;
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uint32_t devarch;
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uint32_t devtype_memtype;
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};
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/**
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* Read the CoreSight registers needed during ROM Table Parsing (RTP).
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*
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* @param ap Pointer to AP containing the component.
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* @param component_base On MEM-AP access method, base address of the component.
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* @param v Pointer to the struct holding the value of registers.
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*
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* @return ERROR_OK on success, else a fault code.
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*/
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static int rtp_read_cs_regs(struct adiv5_ap *ap, target_addr_t component_base,
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struct cs_component_vals *v)
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{
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assert(IS_ALIGNED(component_base, ARM_CS_ALIGN));
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assert(ap && cid && pid);
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assert(ap && v);
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uint32_t cid0, cid1, cid2, cid3;
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uint32_t pid0, pid1, pid2, pid3, pid4;
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int retval;
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int retval = ERROR_OK;
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/* IDs are in last 4K section */
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR0, &pid0);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR1, &pid1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR2, &pid2);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR3, &pid3);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR4, &pid4);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR0, &cid0);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR1, &cid1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR2, &cid2);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR3, &cid3);
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if (retval != ERROR_OK)
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return retval;
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/* sort by offset to gain speed */
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retval = dap_run(ap->dap);
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if (retval != ERROR_OK)
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return retval;
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/*
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* Registers DEVARCH and DEVTYPE are valid on Class 0x9 devices
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* only, but are at offset above 0xf00, so can be read on any device
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* without triggering error. Read them for eventual use on Class 0x9.
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*/
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVARCH, &v->devarch);
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*cid = (cid3 & 0xff) << 24
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/* Same address as ARM_CS_C1_MEMTYPE */
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_C9_DEVTYPE, &v->devtype_memtype);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR4, &pid4);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR0, &pid0);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR1, &pid1);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR2, &pid2);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_PIDR3, &pid3);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR0, &cid0);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR1, &cid1);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR2, &cid2);
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if (retval == ERROR_OK)
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retval = mem_ap_read_u32(ap, component_base + ARM_CS_CIDR3, &cid3);
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if (retval == ERROR_OK)
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retval = dap_run(ap->dap);
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if (retval != ERROR_OK) {
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LOG_DEBUG("Failed read CoreSight registers");
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return retval;
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}
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v->cid = (cid3 & 0xff) << 24
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| (cid2 & 0xff) << 16
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| (cid1 & 0xff) << 8
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| (cid0 & 0xff);
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*pid = (uint64_t)(pid4 & 0xff) << 32
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v->pid = (uint64_t)(pid4 & 0xff) << 32
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| (pid3 & 0xff) << 24
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| (pid2 & 0xff) << 16
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| (pid1 & 0xff) << 8
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@ -1449,10 +1476,9 @@ static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
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static int dap_rom_display(struct command_invocation *cmd,
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struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
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{
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struct cs_component_vals v;
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unsigned int rom_num_entries;
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int retval;
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uint64_t pid;
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uint32_t cid;
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char tabs[16] = "";
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if (depth > 16) {
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@ -1466,29 +1492,29 @@ static int dap_rom_display(struct command_invocation *cmd,
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target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull;
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command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_addr);
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retval = dap_read_part_id(ap, base_addr, &cid, &pid);
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retval = rtp_read_cs_regs(ap, base_addr, &v);
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if (retval != ERROR_OK) {
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command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
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return ERROR_OK; /* Don't abort recursion */
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}
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if (!is_valid_arm_cs_cidr(cid)) {
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command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
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if (!is_valid_arm_cs_cidr(v.cid)) {
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command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, v.cid);
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return ERROR_OK; /* Don't abort recursion */
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}
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/* component may take multiple 4K pages */
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uint32_t size = ARM_CS_PIDR_SIZE(pid);
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uint32_t size = ARM_CS_PIDR_SIZE(v.pid);
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if (size > 0)
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command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size);
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command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
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command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, v.pid);
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const unsigned int class = ARM_CS_CIDR_CLASS(cid);
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const unsigned int part_num = ARM_CS_PIDR_PART(pid);
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unsigned int designer_id = ARM_CS_PIDR_DESIGNER(pid);
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const unsigned int class = ARM_CS_CIDR_CLASS(v.cid);
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const unsigned int part_num = ARM_CS_PIDR_PART(v.pid);
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unsigned int designer_id = ARM_CS_PIDR_DESIGNER(v.pid);
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if (pid & ARM_CS_PIDR_JEDEC) {
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if (v.pid & ARM_CS_PIDR_JEDEC) {
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/* JEP106 code */
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command_print(cmd, "\t\tDesigner is 0x%03x, %s",
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designer_id, jep106_manufacturer(designer_id));
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@ -1504,44 +1530,29 @@ static int dap_rom_display(struct command_invocation *cmd,
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command_print(cmd, "\t\tComponent class is 0x%x, %s", class, class_description[class]);
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if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
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uint32_t memtype;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C1_MEMTYPE, &memtype);
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if (retval != ERROR_OK)
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return retval;
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if (memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
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if (v.devtype_memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
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command_print(cmd, "\t\tMEMTYPE system memory present on bus");
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else
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command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
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rom_num_entries = 960;
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} else if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
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uint32_t devtype;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVTYPE, &devtype);
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if (retval != ERROR_OK)
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return retval;
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retval = dap_devtype_display(cmd, devtype);
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retval = dap_devtype_display(cmd, v.devtype_memtype);
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if (retval != ERROR_OK)
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return retval;
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/* REVISIT also show ARM_CS_C9_DEVID */
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uint32_t devarch;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVARCH, &devarch);
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if (retval != ERROR_OK)
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return retval;
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if ((devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
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if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
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return ERROR_OK;
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unsigned int architect_id = (devarch & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) >> ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT;
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unsigned int revision = (devarch & ARM_CS_C9_DEVARCH_REVISION_MASK) >> ARM_CS_C9_DEVARCH_REVISION_SHIFT;
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command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", devarch,
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jep106_manufacturer(architect_id), class0x9_devarch_description(devarch),
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unsigned int architect_id = (v.devarch & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) >> ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT;
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unsigned int revision = (v.devarch & ARM_CS_C9_DEVARCH_REVISION_MASK) >> ARM_CS_C9_DEVARCH_REVISION_SHIFT;
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command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", v.devarch,
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jep106_manufacturer(architect_id), class0x9_devarch_description(v.devarch),
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revision);
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/* quit if not ROM table */
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if ((devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
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if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
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return ERROR_OK;
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rom_num_entries = 512;
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