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Documentation for mxc NAND flash controller 

Change-Id: I9e552491e8b4737c01e4f8ae2b9a582b6ff2bc5d
Signed-off-by: Erik Ahlén <erik.ahlen@avalonenterprise.com>
Reviewed-on: http://openocd.zylin.com/273
Tested-by: jenkins
Reviewed-by: Mathias Küster <kesmtp@freenet.de>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Erik Ahlén 2011-12-14 13:05:06 +01:00 committed by Spencer Oliver
parent 8901fca027
commit c402c1166b
1 changed files with 21 additions and 0 deletions
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doc/openocd.texi
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@ -5474,6 +5474,27 @@ in the MLC controller mode, but won't change SLC behavior.
@end deffn
@comment current lpc3180 code won't issue 5-byte address cycles
@deffn {NAND Driver} mx3
This driver handles the NAND controller in i.MX31. The mxc driver
should work for this chip aswell.
@end deffn
@deffn {NAND Driver} mxc
This driver handles the NAND controller found in Freescale i.MX
chips. It has support for v1 (i.MX27 and i.MX31) and v2 (i.MX35).
The driver takes 3 extra arguments, chip (@option{mx27},
@option{mx31}, @option{mx35}), ecc (@option{noecc}, @option{hwecc})
and optionally if bad block information should be swapped between
main area and spare area (@option{biswap}), defaults to off.
@example
nand device mx35.nand mxc imx35.cpu mx35 hwecc biswap
@end example
@deffn Command {mxc biswap} bank_num [enable|disable]
Turns on/off bad block information swaping from main area,
without parameter query status.
@end deffn
@end deffn
@deffn {NAND Driver} orion
These controllers require an extra @command{nand device}
parameter: the address of the controller.