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tcl/target: start using the new TPIU/SWO support 

Create the TPIU and SWO device in target config file.
Replace the target event 'trace-config' with the TPIU/SWO event
'post-enable'.
Extend the existing code in the event handler to properly set the
gpio mode and speed to permit synchronous trace.

This patch is not exhaustive of all the targets that have SWO, but
has to be considered as an initial example.

Change-Id: If4bbf364c0d2aef3ae49951e76507a3b1cfd58e7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5859
Tested-by: jenkins
Reviewed-by: Adrian M Negreanu <adrian.negreanu@nxp.com>
This commit is contained in:
Antonio Borneo 2020-10-12 00:12:05 +02:00
parent 184724d14e
commit c945d6e616
3 changed files with 54 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
tcl/target/stm32f4x.cfg
View File

@ -38,6 +38,8 @@ if { [info exists CPUTAPID] } {
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
tpiu create $_CHIPNAME.tpiu -dap stm32f4x.dap -ap-num 0 -baseaddr 0xE0040000
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
@ -89,13 +91,37 @@ $_TARGETNAME configure -event examine-end {
mmw 0xE0042008 0x00001800 0
}
$_TARGETNAME configure -event trace-config {
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0xE0042004 0x00000020 0
proc proc_post_enable {_chipname} {
targets $_chipname.cpu
if { [$_chipname.tpiu cget -protocol] eq "sync" } {
switch [$_chipname.tpiu cget -port-width] {
1 {
mmw 0xE0042004 0x00000060 0x000000c0
mmw 0x40021020 0x00000000 0x0000ff00
mmw 0x40021000 0x000000a0 0x000000f0
mmw 0x40021008 0x000000f0 0x00000000
}
2 {
mmw 0xE0042004 0x000000a0 0x000000c0
mmw 0x40021020 0x00000000 0x000fff00
mmw 0x40021000 0x000002a0 0x000003f0
mmw 0x40021008 0x000003f0 0x00000000
}
4 {
mmw 0xE0042004 0x000000e0 0x000000c0
mmw 0x40021020 0x00000000 0x0fffff00
mmw 0x40021000 0x00002aa0 0x00003ff0
mmw 0x40021008 0x00003ff0 0x00000000
}
}
} else {
mmw 0xE0042004 0x00000020 0x000000c0
}
}
$_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
$_TARGETNAME configure -event reset-init {
# Configure PLL to boost clock to HSI x 4 (64 MHz)
mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)

19
tcl/target/stm32h7x.cfg
View File

@ -77,6 +77,8 @@ if {![using_hla]} {
# STM32H7 provides an APB-AP at access port 2, which allows the access to
# the debug and trace features on the system APB System Debug Bus (APB-D).
target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00E3000
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE00F5000
}
target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
@ -178,13 +180,20 @@ $_CHIPNAME.cpu0 configure -event examine-end {
stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
# DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
}
$_CHIPNAME.cpu0 configure -event trace-config {
# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
# Enable clock for tracing
# DBGMCU_CR |= TRACECLKEN
stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
# RM0399 (id 0x450) M7+M4 with SWO Funnel
# RM0433 (id 0x450) M7 with SWO Funnel
# RM0455 (id 0x480) M7 without SWO Funnel
# RM0468 (id 0x483) M7 without SWO Funnel
# Enable CM7 and CM4 slave ports in SWO trace Funnel
# Works ok also on devices single core and without SWO funnel
# Hack, use stm32h7x_dbgmcu_mmw with big offset to control SWTF
# SWTF_CTRL |= ENS0 | ENS1
stm32h7x_dbgmcu_mmw 0x3000 0x00000003 0
}
$_CHIPNAME.cpu0 configure -event reset-init {

11
tcl/target/stm32mp15x.cfg
View File

@ -64,6 +64,9 @@ cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D800
cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
cti create $_CHIPNAME.cti.cm4 -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
# interface does not work while srst is asserted
# this is target specific, valid for every board
# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
@ -108,9 +111,13 @@ proc detect_cpu1 {} {
if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
}
proc rcc_enable_traceclk {} {
$::_CHIPNAME.ap2 mww 0x5000080c 0x301
}
# FIXME: most of handler below will be removed once reset framework get merged
$_CHIPNAME.ap1 configure -event reset-deassert-pre {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
$_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug}
$_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug;rcc_enable_traceclk}
$_CHIPNAME.cpu0 configure -event reset-deassert-pre {$::_CHIPNAME.cpu0 arp_examine}
$_CHIPNAME.cpu1 configure -event reset-deassert-pre {$::_CHIPNAME.cpu1 arp_examine allow-defer}
$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
@ -118,4 +125,4 @@ $_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_exami
$_CHIPNAME.ap1 configure -event examine-start {dap init}
$_CHIPNAME.ap2 configure -event examine-start {dbgmcu_enable_debug}
$_CHIPNAME.cpu0 configure -event examine-end {detect_cpu1}
$_CHIPNAME.ap2 configure -event examine-end {$::_CHIPNAME.cm4 arp_examine}
$_CHIPNAME.ap2 configure -event examine-end {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}