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Laurentiu Cocanu - memory read/write and exit() error path fixes 

git-svn-id: svn://svn.berlios.de/openocd/trunk@1064 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2008-10-15 11:44:36 +00:00
parent af41e6aac8
commit ccc2e3fe76
15 changed files with 406 additions and 131 deletions
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6
src/flash/at91sam7.c
View File

@ -983,6 +983,7 @@ int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
{
int retval;
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
u32 dst_min_alignment, wcount, bytes_remaining = count;
@ -1033,7 +1034,10 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* Write one block to the PageWriteBuffer */
buffer_pos = (pagen-first_page)*dst_min_alignment;
wcount = CEIL(count,4);
target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);
if((retval = target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos)) != ERROR_OK)
{
return retval;
}
/* Send Write Page command to Flash Controller */
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)

345
src/flash/cfi.c
View File

@ -345,6 +345,7 @@ int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
int cfi_read_intel_pri_ext(flash_bank_t *bank)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
target_t *target = bank->target;
@ -359,9 +360,15 @@ int cfi_read_intel_pri_ext(flash_bank_t *bank)
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("Could not read bank flash bank information");
return ERROR_FLASH_BANK_INVALID;
}
@ -401,6 +408,7 @@ int cfi_read_intel_pri_ext(flash_bank_t *bank)
int cfi_read_spansion_pri_ext(flash_bank_t *bank)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
target_t *target = bank->target;
@ -415,7 +423,10 @@ int cfi_read_spansion_pri_ext(flash_bank_t *bank)
if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("Could not read spansion bank information");
return ERROR_FLASH_BANK_INVALID;
}
@ -462,6 +473,7 @@ int cfi_read_spansion_pri_ext(flash_bank_t *bank)
int cfi_read_atmel_pri_ext(flash_bank_t *bank)
{
int retval;
cfi_atmel_pri_ext_t atmel_pri_ext;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
@ -484,7 +496,10 @@ int cfi_read_atmel_pri_ext(flash_bank_t *bank)
if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("Could not read atmel bank information");
return ERROR_FLASH_BANK_INVALID;
}
@ -664,6 +679,7 @@ int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **
int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
@ -674,17 +690,26 @@ int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
for (i = first; i <= last; i++)
{
cfi_command(bank, 0x20, command);
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xd0, command);
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
bank->sectors[i].is_erased = 1;
else
{
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
@ -692,13 +717,13 @@ int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
return ERROR_OK;
}
int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
@ -708,29 +733,50 @@ int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
for (i = first; i <= last; i++)
{
cfi_command(bank, 0xaa, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x80, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xaa, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x30, command);
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
bank->sectors[i].is_erased = 1;
else
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
@ -738,9 +784,7 @@ int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
}
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
return ERROR_OK;
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_erase(struct flash_bank_s *bank, int first, int last)
@ -780,6 +824,7 @@ int cfi_erase(struct flash_bank_s *bank, int first, int last)
int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
@ -799,19 +844,28 @@ int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
{
cfi_command(bank, 0x60, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (set)
{
cfi_command(bank, 0x01, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
bank->sectors[i].is_protected = 1;
}
else
{
cfi_command(bank, 0xd0, command);
LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
bank->sectors[i].is_protected = 0;
}
@ -826,14 +880,20 @@ int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
u8 block_status;
/* read block lock bit, to verify status */
cfi_command(bank, 0x90, command);
target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
block_status = cfi_get_u8(bank, i, 0x2);
if ((block_status & 0x1) != set)
{
LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
cfi_command(bank, 0x70, command);
target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_intel_wait_status_busy(bank, 10);
if (retry > 10)
@ -859,10 +919,16 @@ int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x60, command);
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x01, command);
target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_intel_wait_status_busy(bank, 100);
}
@ -870,9 +936,7 @@ int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
return ERROR_OK;
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
@ -1485,20 +1549,30 @@ int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address,
int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
cfi_intel_clear_status_register(bank);
cfi_command(bank, 0x40, command);
target->type->write_memory(target, address, bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
target->type->write_memory(target, address, bank->bus_width, 1, word);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
@ -1509,6 +1583,7 @@ int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
@ -1546,11 +1621,17 @@ int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u3
/* Initiate buffer operation _*/
cfi_command(bank, 0xE8, command);
target->type->write_memory(target, address, bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
@ -1558,17 +1639,29 @@ int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u3
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
target->type->write_memory(target, address, bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
{
return retval;
}
/* Commit write operation */
cfi_command(bank, 0xd0, command);
target->type->write_memory(target, address, bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
{
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
@ -1579,26 +1672,42 @@ int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u3
int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
u8 command[8];
cfi_command(bank, 0xaa, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xa0, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
target->type->write_memory(target, address, bank->bus_width, 1, word);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
{
return retval;
}
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
return ERROR_FLASH_OPERATION_FAILED;
@ -1609,6 +1718,7 @@ int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
target_t *target = bank->target;
u8 command[8];
@ -1644,29 +1754,50 @@ int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount,
// Unlock
cfi_command(bank, 0xaa, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
// Buffer load command
cfi_command(bank, 0x25, command);
target->type->write_memory(target, address, bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
/* Write buffer wordcount-1 and data words */
cfi_command(bank, bufferwsize-1, command);
target->type->write_memory(target, address, bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
{
return retval;
}
/* Commit write operation */
cfi_command(bank, 0x29, command);
target->type->write_memory(target, address, bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
return ERROR_FLASH_OPERATION_FAILED;
@ -1755,7 +1886,10 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
for (i = 0; i < align; ++i, ++copy_p)
{
u8 byte;
target->type->read_memory(target, copy_p, 1, 1, &byte);
if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
}
cfi_add_byte(bank, current_word, byte);
}
@ -1771,7 +1905,10 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
{
u8 byte;
target->type->read_memory(target, copy_p, 1, 1, &byte);
if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
}
cfi_add_byte(bank, current_word, byte);
}
@ -1869,9 +2006,15 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* return to read array mode, so we can read from flash again for padding */
cfi_command(bank, 0xf0, current_word);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, current_word);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{
return retval;
}
/* handle unaligned tail bytes */
if (count > 0)
@ -1890,7 +2033,10 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
for (; i < bank->bus_width; ++i, ++copy_p)
{
u8 byte;
target->type->read_memory(target, copy_p, 1, 1, &byte);
if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
{
return retval;
}
cfi_add_byte(bank, current_word, byte);
}
retval = cfi_write_word(bank, current_word, write_p);
@ -1900,11 +2046,12 @@ int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
/* return to read array mode */
cfi_command(bank, 0xf0, current_word);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, current_word);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
return ERROR_OK;
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
}
void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
@ -1979,11 +2126,20 @@ int cfi_probe(struct flash_bank_s *bank)
/* switch to read identifier codes mode ("AUTOSELECT") */
cfi_command(bank, 0xaa, command);
target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x90, command);
target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
if (bank->chip_width == 1)
{
@ -2013,9 +2169,15 @@ int cfi_probe(struct flash_bank_s *bank)
/* switch back to read array mode */
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_fixup(bank, cfi_jedec_fixups);
@ -2032,7 +2194,10 @@ int cfi_probe(struct flash_bank_s *bank)
* SST flashes clearly violate this, and we will consider them incompatbile for now
*/
cfi_command(bank, 0x98, command);
target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
@ -2043,9 +2208,15 @@ int cfi_probe(struct flash_bank_s *bank)
if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
{
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
LOG_ERROR("Could not probe bank");
return ERROR_FLASH_BANK_INVALID;
}
@ -2131,9 +2302,15 @@ int cfi_probe(struct flash_bank_s *bank)
* we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
*/
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
}
/* apply fixups depending on the primary command set */
@ -2205,6 +2382,7 @@ int cfi_auto_probe(struct flash_bank_s *bank)
int cfi_intel_protect_check(struct flash_bank_s *bank)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
@ -2216,7 +2394,10 @@ int cfi_intel_protect_check(struct flash_bank_s *bank)
return ERROR_FLASH_OPERATION_FAILED;
cfi_command(bank, 0x90, command);
target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
for (i = 0; i < bank->num_sectors; i++)
{
@ -2229,13 +2410,12 @@ int cfi_intel_protect_check(struct flash_bank_s *bank)
}
cfi_command(bank, 0xff, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
return ERROR_OK;
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_spansion_protect_check(struct flash_bank_s *bank)
{
int retval;
cfi_flash_bank_t *cfi_info = bank->driver_priv;
cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
target_t *target = bank->target;
@ -2243,13 +2423,22 @@ int cfi_spansion_protect_check(struct flash_bank_s *bank)
int i;
cfi_command(bank, 0xaa, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x55, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
cfi_command(bank, 0x90, command);
target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
{
return retval;
}
for (i = 0; i < bank->num_sectors; i++)
{
@ -2262,9 +2451,7 @@ int cfi_spansion_protect_check(struct flash_bank_s *bank)
}
cfi_command(bank, 0xf0, command);
target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
return ERROR_OK;
return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
}
int cfi_protect_check(struct flash_bank_s *bank)

6
src/flash/lpc2000.c
View File

@ -241,6 +241,7 @@ int lpc2000_build_sector_list(struct flash_bank_s *bank)
*/
int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 result_table[2])
{
int retval;
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
target_t *target = bank->target;
mem_param_t mem_params[2];
@ -263,7 +264,10 @@ int lpc2000_iap_call(flash_bank_t *bank, int code, u32 param_table[5], u32 resul
/* write IAP code to working area */
target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
target->type->write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate);
if((retval = target->type->write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate)) != ERROR_OK)
{
return retval;
}
}
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;

4
src/flash/nand.c
View File

@ -204,10 +204,10 @@ int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, cha
if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
{
/* register flash specific commands */
if (nand_flash_controllers[i]->register_commands(cmd_ctx) != ERROR_OK)
if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
{
LOG_ERROR("couldn't register '%s' commands", args[0]);
exit(-1);
return retval;
}
c = malloc(sizeof(nand_device_t));

4
src/jtag/ft2232.c
View File

@ -410,7 +410,7 @@ int ft2232_send_and_recv(jtag_command_t *first, jtag_command_t *last)
if ((retval = ft2232_write(ft2232_buffer, ft2232_buffer_size, &bytes_written)) != ERROR_OK)
{
LOG_ERROR("couldn't write MPSSE commands to FT2232");
exit(-1);
return retval;
}
#ifdef _DEBUG_USB_IO_
@ -429,7 +429,7 @@ int ft2232_send_and_recv(jtag_command_t *first, jtag_command_t *last)
if ((retval = ft2232_read(ft2232_buffer, ft2232_expect_read, &bytes_read)) != ERROR_OK)
{
LOG_ERROR("couldn't read from FT2232");
exit(-1);
return retval;
}
#ifdef _DEBUG_USB_IO_

7
src/jtag/jtag.c
View File

@ -1720,6 +1720,7 @@ static int default_speed_div(int speed, int *khz)
int handle_interface_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
int i;
int retval;
/* check whether the interface is already configured */
if (jtag_interface)
@ -1738,8 +1739,10 @@ int handle_interface_command(struct command_context_s *cmd_ctx, char *cmd, char
{
if (strcmp(args[0], jtag_interfaces[i]->name) == 0)
{
if (jtag_interfaces[i]->register_commands(cmd_ctx) != ERROR_OK)
exit(-1);
if ((retval = jtag_interfaces[i]->register_commands(cmd_ctx)) != ERROR_OK)
{
return retval;
}
jtag_interface = jtag_interfaces[i];

47
src/target/arm7_9_common.c
View File

@ -217,14 +217,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u32 verify = 0xffffffff;
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
{
return retval;
}
target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify)) != ERROR_OK)
{
return retval;
}
if (verify != arm7_9->arm_bkpt)
{
LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
@ -235,14 +241,20 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u16 verify = 0xffff;
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
{
return retval;
}
target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify)) != ERROR_OK)
{
return retval;
}
if (verify != arm7_9->thumb_bkpt)
{
LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
@ -291,17 +303,29 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u32 current_instr;
/* check that user program as not modified breakpoint instruction */
target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr);
if ((retval = target->type->read_memory(target, breakpoint->address, 4, 1, (u8*)&current_instr)) != ERROR_OK)
{
return retval;
}
if (current_instr==arm7_9->arm_bkpt)
target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
if ((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
else
{
u16 current_instr;
/* check that user program as not modified breakpoint instruction */
target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr);
if ((retval = target->type->read_memory(target, breakpoint->address, 2, 1, (u8*)&current_instr)) != ERROR_OK)
{
return retval;
}
if (current_instr==arm7_9->thumb_bkpt)
target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
if ((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
breakpoint->set = 0;
}
@ -2306,6 +2330,7 @@ int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem
int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int i;
@ -2332,7 +2357,10 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
}
/* write DCC code to working area */
target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
if ((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
{
return retval;
}
}
armv4_5_algorithm_t armv4_5_info;
@ -2348,7 +2376,6 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
//armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params,
// int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, u32 exit_point, int timeout_ms, void *arch_info))
int retval;
dcc_count=count;
dcc_buffer=buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,

5
src/target/arm920t.c
View File

@ -233,6 +233,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
@ -294,10 +295,10 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
arm7_9_execute_sys_speed(target);
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("failed executing JTAG queue, exiting");
exit(-1);
return retval;
}
return ERROR_OK;

22
src/target/cortex_m3.c
View File

@ -810,6 +810,7 @@ void cortex_m3_enable_breakpoints(struct target_s *target)
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
int fp_num=0;
u32 hilo;
@ -851,8 +852,14 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
u8 code[4];
buf_set_u32(code, 0, 32, ARMV7M_T_BKPT(0x11));
target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr);
target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code);
if((retval = target->type->read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
{
return retval;
}
breakpoint->set = 0x11; /* Any nice value but 0 */
}
@ -861,6 +868,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
@ -889,11 +897,17 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr);
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
else
{
target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr);
if((retval = target->type->write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
}
breakpoint->set = 0;

13
src/target/embeddedice.c
View File

@ -222,15 +222,17 @@ int embeddedice_setup(target_t *target)
int embeddedice_get_reg(reg_t *reg)
{
if (embeddedice_read_reg(reg) != ERROR_OK)
int retval;
if ((retval = embeddedice_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
exit(-1);
return retval;
}
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
return retval;
}
return ERROR_OK;
@ -381,12 +383,13 @@ void embeddedice_set_reg(reg_t *reg, u32 value)
int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
embeddedice_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
exit(-1);
return retval;
}
return ERROR_OK;
}

18
src/target/etb.c
View File

@ -160,15 +160,17 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
int etb_get_reg(reg_t *reg)
{
if (etb_read_reg(reg) != ERROR_OK)
int retval;
if ((retval = etb_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
exit(-1);
return retval;
}
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
return retval;
}
return ERROR_OK;
@ -311,10 +313,11 @@ int etb_read_reg(reg_t *reg)
int etb_set_reg(reg_t *reg, u32 value)
{
if (etb_write_reg(reg, value) != ERROR_OK)
int retval;
if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
exit(-1);
return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
@ -326,12 +329,13 @@ int etb_set_reg(reg_t *reg, u32 value)
int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
exit(-1);
return retval;
}
return ERROR_OK;
}

18
src/target/etm.c
View File

@ -311,15 +311,17 @@ int etm_setup(target_t *target)
int etm_get_reg(reg_t *reg)
{
if (etm_read_reg(reg) != ERROR_OK)
int retval;
if ((retval = etm_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
exit(-1);
return retval;
}
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
return retval;
}
return ERROR_OK;
@ -389,10 +391,11 @@ int etm_read_reg(reg_t *reg)
int etm_set_reg(reg_t *reg, u32 value)
{
if (etm_write_reg(reg, value) != ERROR_OK)
int retval;
if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
exit(-1);
return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
@ -404,12 +407,13 @@ int etm_set_reg(reg_t *reg, u32 value)
int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
etm_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if (jtag_execute_queue() != ERROR_OK)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
exit(-1);
return retval;
}
return ERROR_OK;
}

6
src/target/feroceon.c
View File

@ -523,6 +523,7 @@ int feroceon_examine_debug_reason(target_t *target)
int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
@ -579,7 +580,10 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
/* write DCC code to working area */
target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf);
if((retval = target->type->write_memory(target, arm7_9->dcc_working_area->address, 4, dcc_size, dcc_code_buf)) != ERROR_OK)
{
return retval;
}
}
/* backup clobbered processor state */

4
src/target/target.c
View File

@ -533,10 +533,10 @@ int target_init(struct command_context_s *cmd_ctx)
target->type->examine = default_examine;
}
if (target->type->init_target(cmd_ctx, target) != ERROR_OK)
if ((retval = target->type->init_target(cmd_ctx, target)) != ERROR_OK)
{
LOG_ERROR("target '%s' init failed", target->type->name);
exit(-1);
return retval;
}
/* Set up default functions if none are provided by target */

32
src/target/xscale.c
View File

@ -2142,6 +2142,7 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca
int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@ -2186,16 +2187,28 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (breakpoint->length == 4)
{
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
if((retval = target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
target_write_u32(target, breakpoint->address, xscale->arm_bkpt);
if((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
{
return retval;
}
}
else
{
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
if((retval = target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
target_write_u32(target, breakpoint->address, xscale->thumb_bkpt);
if((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
{
return retval;
}
}
breakpoint->set = 1;
}
@ -2242,6 +2255,7 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@ -2276,11 +2290,17 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
/* restore original instruction (kept in target endianness) */
if (breakpoint->length == 4)
{
target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
if((retval = target->type->write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
else
{
target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
if((retval = target->type->write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
{
return retval;
}
}
breakpoint->set = 0;
}