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Cache invalidation when writing to memory

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git-svn-id: svn://svn.berlios.de/openocd/trunk@2708 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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mlu 2009-09-14 22:36:27 +00:00
parent 14dc22612b
commit d4e4d65d28
1 changed files with 18 additions and 0 deletions
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18
src/target/cortex_a8.c
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@ -1253,6 +1253,24 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
exit(-1);
}
/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
/* invalidate I-Cache */
if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
{
/* Invalidate ICache single entry with MVA, repeat this for all cache
lines in the address range, Cortex-A8 has fixed 64 byte line length */
/* Invalidate Cache single entry with MVA to PoU */
for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
}
/* invalidate D-Cache */
if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
/* Invalidate Cache single entry with MVA to PoC */
for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
}
return retval;
}