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tcl: am437x: disable watchdog on reset-end 

sometimes, watchdog might be left running and
it could expire in the middle of a debug session,
to prevent that, just make sure to disable watchdog
on reset-end if current state is 'halted'.

Change-Id: Ib4f2a2321cba17cd8c56ca3ae63114a563a6de90
Tested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Reviewed-on: http://openocd.zylin.com/2615
Tested-by: jenkins
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Felipe Balbi 2015-03-15 23:15:15 -05:00 committed by Paul Fertser
parent 92a01329c9
commit d85a0a6a0c
1 changed files with 29 additions and 0 deletions
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29
tcl/target/am437x.cfg
View File

@ -1,4 +1,5 @@
source [find target/icepick.cfg]
source [find mem_helper.tcl]
###############################################################################
## AM437x Registers ##
@ -481,3 +482,31 @@ target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80
# SRAM: 256K at 0x4030.0000
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000
# Disables watchdog timer after reset otherwise board won't stay in
# halted state.
proc disable_watchdog { } {
global WDT1_WSPR
global WDT1_W_PEND_WSPR
global _TARGETNAME
set curstate [$_TARGETNAME curstate]
if { [string compare $curstate halted] == 0 } {
set WDT_DISABLE_SEQ1 0xaaaa
set WDT_DISABLE_SEQ2 0x5555
mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
# Empty body to make sure this executes as fast as possible.
# We don't want any delays here otherwise romcode might start
# executing and end up changing state of certain IPs.
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
}
}
$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
$_TARGETNAME configure -event reset-end { disable_watchdog }