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tcl/target/stm32l4x: align format/order/comments with stm32f4x 

Change-Id: Ie97bb2f56b582bc735c238af5f160fcb28a61eb0
Signed-off-by: Markus Reiter <me@reitermark.us>
Reviewed-on: https://review.openocd.org/c/openocd/+/6933
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Markus Reiter 2022-04-17 16:01:24 +02:00 committed by Antonio Borneo
parent 7ca770cbf9
commit d8c81d7254
1 changed files with 14 additions and 11 deletions
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25
tcl/target/stm32l4x.cfg
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@ -49,8 +49,9 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
if { [info exists QUADSPI] && $QUADSPI } {
set a [llength [flash list]]
@ -90,6 +91,16 @@ if {![using_hla]} {
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event examine-end {
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}
proc proc_post_enable {_chipname} {
targets $_chipname.cpu
@ -127,6 +138,7 @@ $_TARGETNAME configure -event reset-init {
# 3 WS compliant with VOS == 2 and 24 MHz.
mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
# Boost JTAG frequency
adapter speed 4000
}
@ -135,12 +147,3 @@ $_TARGETNAME configure -event reset-start {
# Reset clock is MSI (4 MHz)
adapter speed 500
}
$_TARGETNAME configure -event examine-end {
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0xE0042004 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0xE0042008 0x00001800 0
}