target: rename cortex_a8 to cortex_a
Rename cortex_a8 target to use a more correct cortex_a name. This also adds a deprecated_name var so that older scripts issue a warning to update the target name. cfg files have also been updated to the new target name. Change-Id: I0eb1429c9281321efeb444b27a662a941a2ab67f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1130 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
This commit is contained in:
Spencer Oliver
Freddie Chopin
parent
b7d2cdc0d4
commit
d9ba56c295
|
|
@ -1878,14 +1878,14 @@ After setting targets, you can define a list of targets working in SMP.
|
|||
@example
|
||||
set _TARGETNAME_1 $_CHIPNAME.cpu1
|
||||
set _TARGETNAME_2 $_CHIPNAME.cpu2
|
||||
target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap \
|
||||
target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap \
|
||||
-coreid 0 -dbgbase $_DAP_DBG1
|
||||
target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap \
|
||||
target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap \
|
||||
-coreid 1 -dbgbase $_DAP_DBG2
|
||||
#define 2 targets working in smp.
|
||||
target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
|
||||
@end example
|
||||
In the above example on cortex_a8, 2 cpus are working in SMP.
|
||||
In the above example on cortex_a, 2 cpus are working in SMP.
|
||||
In SMP only one GDB instance is created and :
|
||||
@itemize @bullet
|
||||
@item a set of hardware breakpoint sets the same breakpoint on all targets in the list.
|
||||
|
|
@ -1896,32 +1896,32 @@ In SMP only one GDB instance is created and :
|
|||
displayed by the GDB session @pxref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.
|
||||
@end itemize
|
||||
|
||||
The SMP behaviour can be disabled/enabled dynamically. On cortex_a8 following
|
||||
The SMP behaviour can be disabled/enabled dynamically. On cortex_a following
|
||||
command have been implemented.
|
||||
@itemize @bullet
|
||||
@item cortex_a8 smp_on : enable SMP mode, behaviour is as described above.
|
||||
@item cortex_a8 smp_off : disable SMP mode, the current target is the one
|
||||
@item cortex_a smp_on : enable SMP mode, behaviour is as described above.
|
||||
@item cortex_a smp_off : disable SMP mode, the current target is the one
|
||||
displayed in the GDB session, only this target is now controlled by GDB
|
||||
session. This behaviour is useful during system boot up.
|
||||
@item cortex_a8 smp_gdb : display/fix the core id displayed in GDB session see
|
||||
@item cortex_a smp_gdb : display/fix the core id displayed in GDB session see
|
||||
following example.
|
||||
@end itemize
|
||||
|
||||
@example
|
||||
>cortex_a8 smp_gdb
|
||||
>cortex_a smp_gdb
|
||||
gdb coreid 0 -> -1
|
||||
#0 : coreid 0 is displayed to GDB ,
|
||||
#-> -1 : next resume triggers a real resume
|
||||
> cortex_a8 smp_gdb 1
|
||||
> cortex_a smp_gdb 1
|
||||
gdb coreid 0 -> 1
|
||||
#0 :coreid 0 is displayed to GDB ,
|
||||
#->1 : next resume displays coreid 1 to GDB
|
||||
> resume
|
||||
> cortex_a8 smp_gdb
|
||||
> cortex_a smp_gdb
|
||||
gdb coreid 1 -> 1
|
||||
#1 :coreid 1 is displayed to GDB ,
|
||||
#->1 : next resume displays coreid 1 to GDB
|
||||
> cortex_a8 smp_gdb -1
|
||||
> cortex_a smp_gdb -1
|
||||
gdb coreid 1 -> -1
|
||||
#1 :coreid 1 is displayed to GDB,
|
||||
#->-1 : next resume triggers a real resume
|
||||
|
|
@ -4064,7 +4064,7 @@ At this writing, the supported CPU types and variants are:
|
|||
@item @code{arm9tdmi} -- this is an ARMv4 core
|
||||
@item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
|
||||
(Support for this is preliminary and incomplete.)
|
||||
@item @code{cortex_a8} -- this is an ARMv7 core with an MMU
|
||||
@item @code{cortex_a} -- this is an ARMv7 core with an MMU
|
||||
@item @code{cortex_m} -- this is an ARMv7 core, supporting only the
|
||||
compact Thumb2 instruction set.
|
||||
@item @code{dragonite} -- resembles arm966e
|
||||
|
|
@ -7300,7 +7300,7 @@ cores @emph{except the ARM1176} use the same six bits.
|
|||
@cindex Debug Access Port
|
||||
@cindex DAP
|
||||
These commands are specific to ARM architecture v7 Debug Access Port (DAP),
|
||||
included on Cortex-M and Cortex-A8 systems.
|
||||
included on Cortex-M and Cortex-A systems.
|
||||
They are available in addition to other core-specific commands that may be available.
|
||||
|
||||
@deffn Command {dap apid} [num]
|
||||
|
|
|
|||
|
|
@ -2746,9 +2746,9 @@ static const struct command_registration cortex_a8_command_handlers[] = {
|
|||
.chain = armv7a_command_handlers,
|
||||
},
|
||||
{
|
||||
.name = "cortex_a8",
|
||||
.name = "cortex_a",
|
||||
.mode = COMMAND_ANY,
|
||||
.help = "Cortex-A8 command group",
|
||||
.help = "Cortex-A command group",
|
||||
.usage = "",
|
||||
.chain = cortex_a8_exec_command_handlers,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -173,3 +173,8 @@ proc cortex_m3 args {
|
|||
echo "DEPRECATED! use 'cortex_m' not 'cortex_m3'"
|
||||
eval cortex_m $args
|
||||
}
|
||||
|
||||
proc cortex_a8 args {
|
||||
echo "DEPRECATED! use 'cortex_a' not 'cortex_a8'"
|
||||
eval cortex_a $args
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ adapter_khz 3000
|
|||
|
||||
$_TARGETNAME configure -event "reset-assert" {
|
||||
echo "Reseting ...."
|
||||
#cortex_a8 dbginit
|
||||
#cortex_a dbginit
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-init { sodimm_init }
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ adapter_khz 3000
|
|||
|
||||
$_TARGETNAME configure -event "reset-assert" {
|
||||
echo "Reseting ...."
|
||||
#cortex_a8 dbginit
|
||||
#cortex_a dbginit
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-init { loco_init }
|
||||
|
|
|
|||
|
|
@ -64,13 +64,13 @@ jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
|
|||
# Cortex A8 target
|
||||
#
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
|
||||
|
||||
# SRAM: 64K at 0x4030.0000; use the first 16K
|
||||
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
|
||||
|
||||
$_TARGETNAME configure -event gdb-attach {
|
||||
cortex_a8 dbginit
|
||||
cortex_a dbginit
|
||||
halt
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -141,7 +141,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
|
|||
|
||||
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
|
||||
|
||||
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
|
||||
# 16K to be used as a scratchpad for OpenOCD.
|
||||
|
|
@ -200,7 +200,7 @@ $_TARGETNAME configure -event gdb-attach {
|
|||
# reset sequence.
|
||||
proc amdm37x_dbginit {target} {
|
||||
# General Cortex A8 debug initialisation
|
||||
cortex_a8 dbginit
|
||||
cortex_a dbginit
|
||||
|
||||
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
|
||||
# access to the signal appears to be implementation specific. TI does not
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
|
|||
|
||||
# GDB target: Cortex-A8, using DAP
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
|
||||
|
||||
# some TCK tycles are required to activate the DEBUG power domain
|
||||
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
|
||||
|
|
@ -41,7 +41,7 @@ jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
|
|||
|
||||
proc imx51_dbginit {target} {
|
||||
# General Cortex A8 debug initialisation
|
||||
cortex_a8 dbginit
|
||||
cortex_a dbginit
|
||||
}
|
||||
|
||||
# Slow speed to be sure it will work
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
|
|||
|
||||
# GDB target: Cortex-A8, using DAP
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.DAP
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
|
||||
|
||||
# some TCK tycles are required to activate the DEBUG power domain
|
||||
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
|
||||
|
|
@ -41,7 +41,7 @@ jtag configure $_CHIPNAME.SJC -event setup "jtag tapenable $_CHIPNAME.DAP"
|
|||
|
||||
proc imx53_dbginit {target} {
|
||||
# General Cortex A8 debug initialisation
|
||||
cortex_a8 dbginit
|
||||
cortex_a dbginit
|
||||
}
|
||||
|
||||
# Slow speed to be sure it will work
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
|
|||
|
||||
# GDB target: Cortex-A8, using DAP
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
|
||||
|
||||
# SRAM: 64K at 0x4020.0000; use the first 16K
|
||||
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
|
||||
|
|
@ -54,7 +54,7 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
|
|||
|
||||
proc omap3_dbginit {target} {
|
||||
# General Cortex A8 debug initialisation
|
||||
cortex_a8 dbginit
|
||||
cortex_a dbginit
|
||||
# Enable DBGU signal for OMAP353x
|
||||
$target mww phys 0x5401d030 0x00002000
|
||||
}
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ set _coreid 0
|
|||
set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
|
||||
echo "Using dbgbase = [format 0x%x $_dbgbase]"
|
||||
|
||||
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
|
||||
-coreid 0 -dbgbase $_dbgbase
|
||||
|
||||
# SRAM: 56KiB at 0x4030.0000
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ set _coreid 0
|
|||
set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
|
||||
echo "Using dbgbase = [format 0x%x $_dbgbase]"
|
||||
|
||||
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
|
||||
-coreid 0 -dbgbase $_dbgbase
|
||||
|
||||
# SRAM: 56KiB at 0x4030.0000
|
||||
|
|
|
|||
|
|
@ -19,12 +19,12 @@ proc ocd_gdb_restart {target_id} {
|
|||
global _SMP
|
||||
targets $_TARGETNAME_1
|
||||
if { [expr ($_SMP == 1)] } {
|
||||
cortex_a8 smp_off
|
||||
cortex_a smp_off
|
||||
}
|
||||
rst_run
|
||||
halt
|
||||
if { [expr ($_SMP == 1)]} {
|
||||
cortex_a8 smp_on
|
||||
cortex_a smp_on
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -202,7 +202,7 @@ if { [info exists DAP_DBG2] } {
|
|||
set _DAP_DBG2 0x801AA000
|
||||
}
|
||||
|
||||
target create $_TARGETNAME_1 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
|
||||
target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
|
||||
|
||||
$_TARGETNAME_1 configure -event gdb-attach {
|
||||
halt
|
||||
|
|
@ -217,7 +217,7 @@ global _TARGETNAME_2
|
|||
set _TARGETNAME_2 $TARGETNAME_2
|
||||
}
|
||||
|
||||
target create $_TARGETNAME_2 cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
|
||||
target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
|
||||
|
||||
$_TARGETNAME_2 configure -event gdb-attach {
|
||||
halt
|
||||
|
|
|
|||
Loading…
Reference in New Issue