dsp5680xx - separate debug from halt
i had assumed two possible halt/debug states: - halted + debug mode - running + not debug mode turns out this one also exists - halted + NOT in debug mode added code to handle this in an appropiate way. Change-Id: Ia0ddcd55d1890c90d100a9e6f5e84ed8dda812a3 Signed-off-by: Rodrigo L. Rosa <rodrigorosa.lg@gmail.com> Reviewed-on: http://openocd.zylin.com/220 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
This commit is contained in:
rodrigo_l_rosa
Øyvind Harboe
parent
6461f7669a
commit
e2fdb1c864
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@ -33,6 +33,13 @@ struct dsp5680xx_common dsp5680xx_context;
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#define _E "DSP5680XX_ERROR:%d\nAt:%s:%d:%s"
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#define err_check(r, c, m) if (r != ERROR_OK) {LOG_ERROR(_E, c, __func__, __LINE__, m); return r; }
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#define err_check_propagate(retval) if (retval != ERROR_OK) return retval;
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#define DEBUG_MSG "Debug mode be enabled to read mem."
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#define DEBUG_FAIL { err_check(ERROR_FAIL, DSP5680XX_ERROR_NOT_IN_DEBUG, DEBUG_MSG) }
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#define CHECK_DBG if (!dsp5680xx_context.debug_mode_enabled) DEBUG_FAIL
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#define HALT_MSG "Target must be halted."
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#define HALT_FAIL { err_check(ERROR_FAIL, DSP5680XX_ERROR_TARGET_RUNNING, HALT_MSG) }
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#define CHECK_HALT(target) if (target->state != TARGET_HALTED) HALT_FAIL
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#define check_halt_and_debug(target) { CHECK_HALT(target); CHECK_DBG; }
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int dsp5680xx_execute_queue(void){
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int retval;
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@ -411,10 +418,7 @@ static int core_rx_lower_data(struct target * target,uint8_t * data_read)
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#define core_move_long_to_y(target,value) dsp5680xx_exe_generic(target,3,0xe417,value&0xffff,value>>16)
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static int core_move_value_to_pc(struct target * target, uint32_t value){
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if (!(target->state == TARGET_HALTED)){
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LOG_ERROR("Target must be halted to move PC. Target state = %d.",target->state);
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return ERROR_TARGET_NOT_HALTED;
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};
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check_halt_and_debug(target);
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int retval;
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retval = dsp5680xx_exe_generic(target,3,0xE71E,value&0xffff,value>>16);
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err_check_propagate(retval);
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@ -544,15 +548,20 @@ static int eonce_enter_debug_mode_without_reset(struct target * target, uint16_t
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err_check_propagate(retval);
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
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err_check_propagate(retval);
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if ((ir_out&JTAG_STATUS_MASK) == JTAG_STATUS_DEBUG)
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target->state = TARGET_HALTED;
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else
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retval = ERROR_FAIL;
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// Verify that debug mode is enabled
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uint16_t data_read_from_dr;
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retval = eonce_read_status_reg(target, &data_read_from_dr);
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err_check_propagate(retval);
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if ((data_read_from_dr&0x30) == 0x30) {
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LOG_DEBUG("EOnCE successfully entered debug mode.");
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target->state = TARGET_HALTED;
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dsp5680xx_context.debug_mode_enabled = true;
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retval = ERROR_OK;
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} else {
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dsp5680xx_context.debug_mode_enabled = false;
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retval = ERROR_TARGET_FAILURE;
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/**
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* No error msg here, since there is still hope with full halting sequence
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@ -642,6 +651,12 @@ static int eonce_enter_debug_mode(struct target * target, uint16_t * eonce_statu
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retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
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err_check_propagate(retval);
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}
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if ((ir_out&JTAG_STATUS_MASK) == JTAG_STATUS_DEBUG)
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target->state = TARGET_HALTED;
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else {
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retval = ERROR_FAIL;
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err_check(retval, DSP5680XX_ERROR_HALT, "Failed to halt target.");
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}
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for(int i = 0; i<3; i++){
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instr_16 = 0x86;
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@ -656,7 +671,7 @@ static int eonce_enter_debug_mode(struct target * target, uint16_t * eonce_statu
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err_check_propagate(retval);
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if((data_read_from_dr&0x30) == 0x30){
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LOG_DEBUG("EOnCE successfully entered debug mode.");
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target->state = TARGET_HALTED;
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dsp5680xx_context.debug_mode_enabled = true;
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retval = ERROR_OK;
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}else{
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const char *msg = "Failed to set EOnCE module to debug mode";
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@ -702,13 +717,14 @@ static int dsp5680xx_target_create(struct target *target, Jim_Interp * interp){
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static int dsp5680xx_init_target(struct command_context *cmd_ctx, struct target *target){
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dsp5680xx_context.stored_pc = 0;
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dsp5680xx_context.flush = 1;
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dsp5680xx_context.debug_mode_enabled = false;
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LOG_DEBUG("target initiated!");
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//TODO core tap must be enabled before running these commands, currently this is done in the .cfg tcl script.
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return ERROR_OK;
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}
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static int dsp5680xx_arch_state(struct target *target){
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LOG_USER("%s not implemented yet.",__FUNCTION__);
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LOG_USER("%s not implemented yet.", __func__);
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return ERROR_OK;
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}
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@ -729,19 +745,26 @@ static int dsp5680xx_deassert_reset(struct target *target){
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static int dsp5680xx_halt(struct target *target){
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int retval;
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uint16_t eonce_status = 0xbeef;
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if(target->state == TARGET_HALTED){
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LOG_USER("Target already halted.");
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if ((target->state == TARGET_HALTED) && (dsp5680xx_context.debug_mode_enabled)) {
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LOG_USER("Target already halted and in debug mode.");
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return ERROR_OK;
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} else {
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if (target->state == TARGET_HALTED)
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LOG_USER("Target already halted, re attempting to enter debug mode.");
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}
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retval = eonce_enter_debug_mode(target,&eonce_status);
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err_check_propagate(retval);
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retval = eonce_pc_store(target);
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err_check_propagate(retval);
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//TODO is it useful to store the pc?
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if (dsp5680xx_context.debug_mode_enabled) {
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retval = eonce_pc_store(target);
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err_check_propagate(retval);
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}
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return retval;
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}
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static int dsp5680xx_poll(struct target *target){
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static int dsp5680xx_poll(struct target *target)
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{
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int retval;
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uint8_t jtag_status;
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uint8_t eonce_status;
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@ -754,7 +777,8 @@ static int dsp5680xx_poll(struct target *target){
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err_check_propagate(retval);
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eonce_status = (uint8_t) read_tmp;
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if ((eonce_status&EONCE_STAT_MASK) != DSP5680XX_ONCE_OSCR_DEBUG_M) {
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LOG_WARNING("%s: Failed to put EOnCE in debug mode. Is flash locked?...",__FUNCTION__);
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const char *msg = "%s: Failed to put EOnCE in debug mode.Flash locked?...";
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LOG_WARNING(msg, __func__);
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return ERROR_TARGET_FAILURE;
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} else {
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target->state = TARGET_HALTED;
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@ -768,7 +792,8 @@ static int dsp5680xx_poll(struct target *target){
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retval = eonce_exit_debug_mode(target, &eonce_status);
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err_check_propagate(retval);
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if ((eonce_status&EONCE_STAT_MASK) != DSP5680XX_ONCE_OSCR_NORMAL_M) {
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LOG_WARNING("%s: JTAG running, but cannot make EOnCE run. Try resetting...",__FUNCTION__);
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const char *msg = "%s: JTAG running, but EOnCE run failed.Try resetting..";
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LOG_WARNING(msg, __func__);
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return ERROR_TARGET_FAILURE;
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} else {
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target->state = TARGET_RUNNING;
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@ -788,24 +813,27 @@ static int dsp5680xx_poll(struct target *target){
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return ERROR_OK;
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}
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if (jtag_status == JTAG_STATUS_DEAD) {
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LOG_ERROR("%s: Cannot communicate with JTAG. Check connection...",__FUNCTION__);
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LOG_ERROR("%s: Cannot communicate with JTAG. Check connection...", __func__);
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target->state = TARGET_UNKNOWN;
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return ERROR_TARGET_FAILURE;
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};
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if (target->state == TARGET_UNKNOWN) {
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LOG_ERROR("%s: Target status invalid - communication failure",__FUNCTION__);
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LOG_ERROR("%s: Target status invalid - communication failure", __func__);
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return ERROR_TARGET_FAILURE;
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};
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return ERROR_OK;
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}
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static int dsp5680xx_resume(struct target *target, int current, uint32_t address,int handle_breakpoints, int debug_execution){
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static int dsp5680xx_resume(struct target *target, int current, uint32_t address, int hb, int d)
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{
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if (target->state == TARGET_RUNNING) {
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LOG_USER("Target already running.");
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return ERROR_OK;
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}
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int retval;
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uint8_t eonce_status;
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uint8_t jtag_status;
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if (dsp5680xx_context.debug_mode_enabled) {
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if (!current) {
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retval = core_move_value_to_pc(target, address);
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err_check_propagate(retval);
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@ -820,11 +848,36 @@ static int dsp5680xx_resume(struct target *target, int current, uint32_t address
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}
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if (retry == 0) {
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retval = ERROR_TARGET_FAILURE;
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err_check(retval, DSP5680XX_ERROR_RESUME, "Failed to resume...");
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err_check(retval, DSP5680XX_ERROR_EXIT_DEBUG_MODE, "Failed to exit debug mode...");
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} else {
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target->state = TARGET_RUNNING;
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dsp5680xx_context.debug_mode_enabled = false;
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}
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LOG_DEBUG("EOnCE status: 0x%02X.", eonce_status);
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} else {
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/**
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* If debug mode was not enabled but target was halted, then it is most likely that
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* access to eonce registers is locked.
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* Reset target to make it run again.
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*/
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jtag_add_reset(0, 1);
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jtag_add_sleep(TIME_DIV_FREESCALE*200*1000);
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retval = reset_jtag();
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err_check(retval, DSP5680XX_ERROR_JTAG_RESET, "Failed to reset JTAG state machine");
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jtag_add_sleep(TIME_DIV_FREESCALE*100*1000);
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jtag_add_reset(0, 0);
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jtag_add_sleep(TIME_DIV_FREESCALE*300*1000);
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retval = dsp5680xx_jtag_status(target, &jtag_status);
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err_check_propagate(retval);
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if ((jtag_status&JTAG_STATUS_MASK) == JTAG_STATUS_NORMAL) {
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target->state = TARGET_RUNNING;
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dsp5680xx_context.debug_mode_enabled = false;
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} else {
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retval = ERROR_TARGET_FAILURE;
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err_check(retval, DSP5680XX_ERROR_RESUME, "Failed to resume target");
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}
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}
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return ERROR_OK;
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}
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@ -834,7 +887,7 @@ static int dsp5680xx_resume(struct target *target, int current, uint32_t address
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/**
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* The value of @address determines if it corresponds to P: (program) or X: (data) memory. If the address is over 0x200000 then it is considered X: memory, and @pmem = 0.
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* The value of @address determines if it corresponds to P: (program) or X: (dat) memory. If the address is over 0x200000 then it is considered X: memory, and @pmem = 0.
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* The special case of 0xFFXXXX is not modified, since it allows to read out the memory mapped EOnCE registers.
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*
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* @param address
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@ -842,9 +895,12 @@ static int dsp5680xx_resume(struct target *target, int current, uint32_t address
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*
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* @return
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*/
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static int dsp5680xx_convert_address(uint32_t * address, int * pmem){
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// Distinguish data memory (x:) from program memory (p:) by the address.
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// Addresses over S_FILE_DATA_OFFSET are considered (x:) memory.
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static int dsp5680xx_convert_address(uint32_t *address, int *pmem)
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{
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/**
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* Distinguish data memory (x) from program memory (p) by the address.
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* Addresses over S_FILE_DATA_OFFSET are considered (x) memory.
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*/
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if (*address >= S_FILE_DATA_OFFSET) {
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*pmem = 0;
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if (((*address)&0xff0000) != 0xff0000)
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@ -853,7 +909,10 @@ static int dsp5680xx_convert_address(uint32_t * address, int * pmem){
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return ERROR_OK;
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}
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static int dsp5680xx_read_16_single(struct target * target, uint32_t address, uint8_t * data_read, int r_pmem){
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static int dsp5680xx_read_16_single(struct target *t, uint32_t a, uint8_t *data_read, int r_pmem)
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{
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struct target *target = t;
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uint32_t address = a;
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int retval;
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retval = core_move_long_to_r0(target,address);
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err_check_propagate(retval);
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@ -869,13 +928,16 @@ static int dsp5680xx_read_16_single(struct target * target, uint32_t address, ui
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// at this point the data i want is at the reg eonce can read
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retval = core_rx_lower_data(target,data_read);
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err_check_propagate(retval);
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LOG_DEBUG("%s: Data read from 0x%06X: 0x%02X%02X",__FUNCTION__, address,data_read[1],data_read[0]);
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LOG_DEBUG("%s:Data read from 0x%06X: 0x%02X%02X", __func__, address, data_read[1], data_read[0]);
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return retval;
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}
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static int dsp5680xx_read_32_single(struct target * target, uint32_t address, uint8_t * data_read, int r_pmem){
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static int dsp5680xx_read_32_single(struct target *t, uint32_t a, uint8_t *data_read, int r_pmem)
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{
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struct target *target = t;
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uint32_t address = a;
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int retval;
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address = (address & 0xFFFFFE);
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address = (address & 0xFFFFF);
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// Get data to an intermediate register
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retval = core_move_long_to_r0(target,address);
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err_check_propagate(retval);
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@ -906,11 +968,13 @@ static int dsp5680xx_read_32_single(struct target * target, uint32_t address, ui
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return retval;
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}
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static int dsp5680xx_read(struct target * target, uint32_t address, unsigned size, unsigned count, uint8_t * buffer){
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if(target->state != TARGET_HALTED){
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LOG_USER("Target must be halted.");
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return ERROR_FAIL;
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}
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static int dsp5680xx_read(struct target *t, uint32_t a, unsigned size, unsigned count, uint8_t *buf)
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{
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struct target *target = t;
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uint32_t address = a;
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uint8_t *buffer = buf;
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check_halt_and_debug(target);
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int retval = ERROR_OK;
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int pmem = 1;
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@ -927,9 +991,8 @@ static int dsp5680xx_read(struct target * target, uint32_t address, unsigned siz
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}
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switch (size) {
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case 1:
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if(!(i%2)){
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if (!(i%2))
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retval = dsp5680xx_read_16_single(target, address + i/2, buffer + i, pmem);
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}
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break;
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case 2:
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retval = dsp5680xx_read_16_single(target, address + i, buffer+2*i, pmem);
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@ -938,7 +1001,7 @@ static int dsp5680xx_read(struct target * target, uint32_t address, unsigned siz
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retval = dsp5680xx_read_32_single(target, address + 2*i, buffer + 4*i, pmem);
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break;
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default:
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LOG_USER("%s: Invalid read size.",__FUNCTION__);
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LOG_USER("%s: Invalid read size.", __func__);
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break;
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}
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err_check_propagate(retval);
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@ -952,7 +1015,10 @@ static int dsp5680xx_read(struct target * target, uint32_t address, unsigned siz
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return retval;
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}
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static int dsp5680xx_write_16_single(struct target *target, uint32_t address, uint16_t data, uint8_t w_pmem){
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static int dsp5680xx_write_16_single(struct target *t, uint32_t a, uint16_t data, uint8_t w_pmem)
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{
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struct target *target = t;
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uint32_t address = a;
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int retval = 0;
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retval = core_move_long_to_r0(target,address);
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err_check_propagate(retval);
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@ -968,8 +1034,11 @@ static int dsp5680xx_write_16_single(struct target *target, uint32_t address, ui
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return retval;
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}
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static int dsp5680xx_write_32_single(struct target *target, uint32_t address, uint32_t data, int w_pmem){
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int retval = 0;
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static int dsp5680xx_write_32_single(struct target *t, uint32_t a, uint32_t data, int w_pmem)
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{
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struct target *target = t;
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uint32_t address = a;
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int retval = ERROR_OK;
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retval = core_move_long_to_r0(target, address);
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err_check_propagate(retval);
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retval = core_move_long_to_y(target, data);
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@ -987,11 +1056,12 @@ static int dsp5680xx_write_32_single(struct target *target, uint32_t address, ui
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return retval;
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}
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static int dsp5680xx_write_8(struct target * target, uint32_t address, uint32_t count, const uint8_t * data, int pmem){
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if(target->state != TARGET_HALTED){
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LOG_ERROR("%s: Target must be halted.",__FUNCTION__);
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return ERROR_OK;
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};
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static int dsp5680xx_write_8(struct target *t, uint32_t a, uint32_t c, const uint8_t *d, int pmem)
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{
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struct target *target = t;
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uint32_t address = a;
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uint32_t count = c;
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const uint8_t *data = d;
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int retval = 0;
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uint16_t data_16;
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uint32_t iter;
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@ -1005,7 +1075,7 @@ static int dsp5680xx_write_8(struct target * target, uint32_t address, uint32_t
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data_16 = (data[2*iter]|(data[2*iter+1] << 8));
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retval = dsp5680xx_write_16_single(target, address+iter, data_16, pmem);
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if (retval != ERROR_OK) {
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LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__,address);
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LOG_ERROR("%s: Could not write to p:0x%04X", __func__, address);
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dsp5680xx_context.flush = 1;
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return retval;
|
||||
}
|
||||
|
|
@ -1020,7 +1090,7 @@ static int dsp5680xx_write_8(struct target * target, uint32_t address, uint32_t
|
|||
retval = dsp5680xx_read(target, address+iter, 1, 1, (uint8_t *)&data_old);
|
||||
err_check_propagate(retval);
|
||||
if (count == 1)
|
||||
data_old=(((data_old&0xff)<<8)|data[0]);// preserve upper byte
|
||||
data_old = (((data_old&0xff)<<8)|data[0]);/* preserve upper byte */
|
||||
else
|
||||
data_old = (((data_old&0xff)<<8)|data[2*iter+1]);
|
||||
retval = dsp5680xx_write_16_single(target, address+iter, data_old, pmem);
|
||||
|
|
@ -1029,12 +1099,13 @@ static int dsp5680xx_write_8(struct target * target, uint32_t address, uint32_t
|
|||
return retval;
|
||||
}
|
||||
|
||||
static int dsp5680xx_write_16(struct target * target, uint32_t address, uint32_t count, const uint8_t * data, int pmem){
|
||||
static int dsp5680xx_write_16(struct target *t, uint32_t a, uint32_t c, const uint8_t *d, int pmem)
|
||||
{
|
||||
struct target *target = t;
|
||||
uint32_t address = a;
|
||||
uint32_t count = c;
|
||||
const uint8_t *data = d;
|
||||
int retval = ERROR_OK;
|
||||
if(target->state != TARGET_HALTED){
|
||||
retval = ERROR_TARGET_NOT_HALTED;
|
||||
err_check(retval, DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING, "Target must be halted.");
|
||||
};
|
||||
uint32_t iter;
|
||||
int counter = FLUSH_COUNT_READ_WRITE;
|
||||
|
||||
|
|
@ -1045,7 +1116,7 @@ static int dsp5680xx_write_16(struct target * target, uint32_t address, uint32_t
|
|||
}
|
||||
retval = dsp5680xx_write_16_single(target, address+iter, data[iter], pmem);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__,address);
|
||||
LOG_ERROR("%s: Could not write to p:0x%04X", __func__, address);
|
||||
dsp5680xx_context.flush = 1;
|
||||
return retval;
|
||||
}
|
||||
|
|
@ -1055,12 +1126,13 @@ static int dsp5680xx_write_16(struct target * target, uint32_t address, uint32_t
|
|||
return retval;
|
||||
}
|
||||
|
||||
static int dsp5680xx_write_32(struct target * target, uint32_t address, uint32_t count, const uint8_t * data, int pmem){
|
||||
static int dsp5680xx_write_32(struct target *t, uint32_t a, uint32_t c, const uint8_t *d, int pmem)
|
||||
{
|
||||
struct target *target = t;
|
||||
uint32_t address = a;
|
||||
uint32_t count = c;
|
||||
const uint8_t *data = d;
|
||||
int retval = ERROR_OK;
|
||||
if(target->state != TARGET_HALTED){
|
||||
retval = ERROR_TARGET_NOT_HALTED;
|
||||
err_check(retval, DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING, "Target must be halted.");
|
||||
};
|
||||
uint32_t iter;
|
||||
int counter = FLUSH_COUNT_READ_WRITE;
|
||||
|
||||
|
|
@ -1071,7 +1143,7 @@ static int dsp5680xx_write_32(struct target * target, uint32_t address, uint32_t
|
|||
}
|
||||
retval = dsp5680xx_write_32_single(target, address+(iter<<1), data[iter], pmem);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("%s: Could not write to p:0x%04X",__FUNCTION__,address);
|
||||
LOG_ERROR("%s: Could not write to p:0x%04X", __func__, address);
|
||||
dsp5680xx_context.flush = 1;
|
||||
return retval;
|
||||
}
|
||||
|
|
@ -1083,7 +1155,8 @@ static int dsp5680xx_write_32(struct target * target, uint32_t address, uint32_t
|
|||
|
||||
/**
|
||||
* Writes @buffer to memory.
|
||||
* The parameter @address determines whether @buffer should be written to P: (program) memory or X: (data) memory.
|
||||
* The parameter @address determines whether @buffer should be written to
|
||||
* P: (program) memory or X: (dat) memory.
|
||||
*
|
||||
* @param target
|
||||
* @param address
|
||||
|
|
@ -1093,11 +1166,16 @@ static int dsp5680xx_write_32(struct target * target, uint32_t address, uint32_t
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static int dsp5680xx_write(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t * buffer){
|
||||
//TODO Cannot write 32bit to odd address, will write 0x12345678 as 0x5678 0x0012
|
||||
if(target->state != TARGET_HALTED){
|
||||
err_check(ERROR_FAIL, DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING, "Target must be halted.");
|
||||
}
|
||||
static int dsp5680xx_write(struct target *t, uint32_t a, uint32_t s, uint32_t c, const uint8_t *b)
|
||||
{
|
||||
/* TODO Cannot write 32bit to odd address, will write 0x12345678 as 0x5678 0x0012 */
|
||||
struct target *target = t;
|
||||
uint32_t address = a;
|
||||
uint32_t count = c;
|
||||
uint8_t const *buffer = b;
|
||||
uint32_t size = s;
|
||||
check_halt_and_debug(target);
|
||||
|
||||
int retval = 0;
|
||||
int p_mem = 1;
|
||||
retval = dsp5680xx_convert_address(&address, &p_mem);
|
||||
|
|
@ -1121,17 +1199,16 @@ static int dsp5680xx_write(struct target *target, uint32_t address, uint32_t siz
|
|||
return retval;
|
||||
}
|
||||
|
||||
static int dsp5680xx_bulk_write_memory(struct target * target,uint32_t address, uint32_t aligned, const uint8_t * buffer){
|
||||
static int dsp5680xx_bulk_write_memory(struct target *t, uint32_t a, uint32_t al, const uint8_t *b)
|
||||
{
|
||||
LOG_ERROR("Not implemented yet.");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
static int dsp5680xx_write_buffer(struct target * target, uint32_t address, uint32_t size, const uint8_t * buffer){
|
||||
if(target->state != TARGET_HALTED){
|
||||
LOG_USER("Target must be halted.");
|
||||
return ERROR_OK;
|
||||
}
|
||||
return dsp5680xx_write(target, address, 1, size, buffer);
|
||||
static int dsp5680xx_write_buffer(struct target *t, uint32_t a, uint32_t size, const uint8_t *b)
|
||||
{
|
||||
check_halt_and_debug(t);
|
||||
return dsp5680xx_write(t, a, 1, size, b);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1144,13 +1221,11 @@ static int dsp5680xx_write_buffer(struct target * target, uint32_t address, uint
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static int dsp5680xx_read_buffer(struct target * target, uint32_t address, uint32_t size, uint8_t * buffer){
|
||||
if(target->state != TARGET_HALTED){
|
||||
LOG_USER("Target must be halted.");
|
||||
return ERROR_OK;
|
||||
}
|
||||
// The "/2" solves the byte/word addressing issue.
|
||||
return dsp5680xx_read(target,address,2,size/2,buffer);
|
||||
static int dsp5680xx_read_buffer(struct target *t, uint32_t a, uint32_t size, uint8_t *buf)
|
||||
{
|
||||
check_halt_and_debug(t);
|
||||
/* The "/2" solves the byte/word addressing issue.*/
|
||||
return dsp5680xx_read(t, a, 2, size/2, buf);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1164,7 +1239,8 @@ static int dsp5680xx_read_buffer(struct target * target, uint32_t address, uint3
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static int dsp5680xx_checksum_memory(struct target * target, uint32_t address, uint32_t size, uint32_t * checksum){
|
||||
static int dsp5680xx_checksum_memory(struct target *t, uint32_t a, uint32_t s, uint32_t *checksum)
|
||||
{
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
|
|
@ -1177,7 +1253,8 @@ static int dsp5680xx_checksum_memory(struct target * target, uint32_t address, u
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static int perl_crc(uint8_t * buff8,uint32_t word_count){
|
||||
static int perl_crc(uint8_t *buff8, uint32_t word_count)
|
||||
{
|
||||
uint16_t checksum = 0xffff;
|
||||
uint16_t data,fbmisr;
|
||||
uint32_t i;
|
||||
|
|
@ -1196,13 +1273,14 @@ static int perl_crc(uint8_t * buff8,uint32_t word_count){
|
|||
}
|
||||
|
||||
/**
|
||||
* Resets the SIM. (System Integration Module).
|
||||
* Resets the SIM. (System Integration Modul).
|
||||
*
|
||||
* @param target
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_SIM_reset(struct target * target){
|
||||
int dsp5680xx_f_SIM_reset(struct target *target)
|
||||
{
|
||||
int retval = ERROR_OK;
|
||||
uint16_t sim_cmd = SIM_CMD_RESET;
|
||||
uint32_t sim_addr;
|
||||
|
|
@ -1215,13 +1293,14 @@ int dsp5680xx_f_SIM_reset(struct target * target){
|
|||
}
|
||||
|
||||
/**
|
||||
* Halts the core and resets the SIM. (System Integration Module).
|
||||
* Halts the core and resets the SIM. (System Integration Modul).
|
||||
*
|
||||
* @param target
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
static int dsp5680xx_soft_reset_halt(struct target *target){
|
||||
static int dsp5680xx_soft_reset_halt(struct target *target)
|
||||
{
|
||||
//TODO is this what this function is expected to do...?
|
||||
int retval;
|
||||
retval = dsp5680xx_halt(target);
|
||||
|
|
@ -1233,10 +1312,7 @@ static int dsp5680xx_soft_reset_halt(struct target *target){
|
|||
|
||||
int dsp5680xx_f_protect_check(struct target * target, uint16_t * protected) {
|
||||
int retval;
|
||||
if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
|
||||
retval = dsp5680xx_halt(target);
|
||||
err_check_propagate(retval);
|
||||
}
|
||||
check_halt_and_debug(target);
|
||||
if (protected == NULL) {
|
||||
const char *msg = "NULL pointer not valid.";
|
||||
err_check(ERROR_FAIL, DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS, msg);
|
||||
|
|
@ -1247,18 +1323,26 @@ int dsp5680xx_f_protect_check(struct target * target, uint16_t * protected) {
|
|||
}
|
||||
|
||||
/**
|
||||
* Executes a command on the FM module. Some commands use the parameters @address and @data, others ignore them.
|
||||
* Executes a command on the FM module.
|
||||
* Some commands use the parameters @address and @data, others ignore them.
|
||||
*
|
||||
* @param target
|
||||
* @param command Command to execute.
|
||||
* @param address Command parameter.
|
||||
* @param data Command parameter.
|
||||
* @param hfm_ustat FM status register.
|
||||
* @param pmem Address is P: (program) memory (@pmem==1) or X: (data) memory (@pmem==0)
|
||||
* @param pmem Address is P: (program) memory (@pmem==1) or X: (dat) memory (@pmem==0)
|
||||
*
|
||||
* @return
|
||||
*/
|
||||
static int dsp5680xx_f_execute_command(struct target * target, uint16_t command, uint32_t address, uint32_t data, uint16_t * hfm_ustat, int pmem){
|
||||
static int dsp5680xx_f_ex(struct target *t, uint16_t c, uint32_t a, uint32_t d, uint16_t *h, int p)
|
||||
{
|
||||
struct target *target = t;
|
||||
uint32_t command = c;
|
||||
uint32_t address = a;
|
||||
uint32_t data = d;
|
||||
uint16_t *hfm_ustat = h;
|
||||
int pmem = p;
|
||||
int retval;
|
||||
retval = core_load_TX_RX_high_addr_to_r0(target);
|
||||
err_check_propagate(retval);
|
||||
|
|
@ -1343,7 +1427,8 @@ static int dsp5680xx_f_execute_command(struct target * target, uint16_t command,
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static int set_fm_ck_div(struct target * target){
|
||||
static int set_fm_ck_div(struct target *target)
|
||||
{
|
||||
uint8_t i[2];
|
||||
int retval;
|
||||
retval = core_move_long_to_r2(target,HFM_BASE_ADDR);
|
||||
|
|
@ -1391,30 +1476,41 @@ static int set_fm_ck_div(struct target * target){
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static int dsp5680xx_f_signature(struct target * target, uint32_t address, uint32_t words, uint16_t * signature){
|
||||
static int dsp5680xx_f_signature(struct target *t, uint32_t a, uint32_t words, uint16_t * signature)
|
||||
{
|
||||
struct target *target = t;
|
||||
uint32_t address = a;
|
||||
int retval;
|
||||
uint16_t hfm_ustat;
|
||||
if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
|
||||
if (!dsp5680xx_context.debug_mode_enabled) {
|
||||
retval = eonce_enter_debug_mode_without_reset(target, NULL);
|
||||
err_check_propagate(retval);
|
||||
/**
|
||||
* Generate error here, since it is not done in eonce_enter_debug_mode_without_reset
|
||||
*/
|
||||
err_check(retval, DSP5680XX_ERROR_HALT, "Failed to halt target.");
|
||||
}
|
||||
retval = dsp5680xx_f_execute_command(target,HFM_CALCULATE_DATA_SIGNATURE,address,words,&hfm_ustat,1);
|
||||
retval = dsp5680xx_f_ex(target, HFM_CALCULATE_DATA_SIGNATURE, address, words, &hfm_ustat, 1);
|
||||
err_check_propagate(retval);
|
||||
retval = dsp5680xx_read_16_single(target, HFM_BASE_ADDR|HFM_DATA, (uint8_t *)signature, 0);
|
||||
return retval;
|
||||
}
|
||||
|
||||
int dsp5680xx_f_erase_check(struct target * target, uint8_t * erased,uint32_t sector){
|
||||
int dsp5680xx_f_erase_check(struct target *target, uint8_t *erased, uint32_t sector)
|
||||
{
|
||||
int retval;
|
||||
uint16_t hfm_ustat;
|
||||
if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
|
||||
uint32_t tmp;
|
||||
if (!dsp5680xx_context.debug_mode_enabled) {
|
||||
retval = dsp5680xx_halt(target);
|
||||
err_check_propagate(retval);
|
||||
}
|
||||
retval = set_fm_ck_div(target);
|
||||
err_check_propagate(retval);
|
||||
// Check if chip is already erased.
|
||||
retval = dsp5680xx_f_execute_command(target,HFM_ERASE_VERIFY,HFM_FLASH_BASE_ADDR+sector*HFM_SECTOR_SIZE/2,0,&hfm_ustat,1); // blank check
|
||||
/**
|
||||
* Check if chip is already erased.
|
||||
*/
|
||||
tmp = HFM_FLASH_BASE_ADDR+sector*HFM_SECTOR_SIZE/2;
|
||||
retval = dsp5680xx_f_ex(target, HFM_ERASE_VERIFY, tmp, 0, &hfm_ustat, 1);
|
||||
err_check_propagate(retval);
|
||||
if (erased != NULL)
|
||||
*erased = (uint8_t)(hfm_ustat&HFM_USTAT_MASK_BLANK);
|
||||
|
|
@ -1430,9 +1526,11 @@ int dsp5680xx_f_erase_check(struct target * target, uint8_t * erased,uint32_t se
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static int erase_sector(struct target * target, int sector, uint16_t * hfm_ustat){
|
||||
static int erase_sector(struct target *target, int sector, uint16_t *hfm_ustat)
|
||||
{
|
||||
int retval;
|
||||
retval = dsp5680xx_f_execute_command(target,HFM_PAGE_ERASE,HFM_FLASH_BASE_ADDR+sector*HFM_SECTOR_SIZE/2,0,hfm_ustat,1);
|
||||
uint32_t tmp = HFM_FLASH_BASE_ADDR+sector*HFM_SECTOR_SIZE/2;
|
||||
retval = dsp5680xx_f_ex(target, HFM_PAGE_ERASE, tmp, 0, hfm_ustat, 1);
|
||||
err_check_propagate(retval);
|
||||
return retval;
|
||||
}
|
||||
|
|
@ -1445,15 +1543,17 @@ static int erase_sector(struct target * target, int sector, uint16_t * hfm_ustat
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
static int mass_erase(struct target * target, uint16_t * hfm_ustat){
|
||||
static int mass_erase(struct target *target, uint16_t *hfm_ustat)
|
||||
{
|
||||
int retval;
|
||||
retval = dsp5680xx_f_execute_command(target,HFM_MASS_ERASE,0,0,hfm_ustat,1);
|
||||
retval = dsp5680xx_f_ex(target, HFM_MASS_ERASE, 0, 0, hfm_ustat, 1);
|
||||
return retval;
|
||||
}
|
||||
|
||||
int dsp5680xx_f_erase(struct target * target, int first, int last){
|
||||
int dsp5680xx_f_erase(struct target *target, int first, int last)
|
||||
{
|
||||
int retval;
|
||||
if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
|
||||
if (!dsp5680xx_context.debug_mode_enabled) {
|
||||
retval = dsp5680xx_halt(target);
|
||||
err_check_propagate(retval);
|
||||
}
|
||||
|
|
@ -1471,7 +1571,7 @@ int dsp5680xx_f_erase(struct target * target, int first, int last){
|
|||
uint16_t hfm_ustat;
|
||||
int do_mass_erase = ((!(first|last)) || ((first==0)&&(last == (HFM_SECTOR_COUNT-1))));
|
||||
if (do_mass_erase) {
|
||||
//Mass erase
|
||||
/* Mass erase */
|
||||
retval = mass_erase(target, &hfm_ustat);
|
||||
err_check_propagate(retval);
|
||||
} else {
|
||||
|
|
@ -1535,18 +1635,27 @@ const uint16_t pgm_write_pflash[] = {0x8A46, 0x0013, 0x807D, 0xE700,\
|
|||
0x0013, 0x0010, 0xA961};
|
||||
const uint32_t pgm_write_pflash_length = 31;
|
||||
|
||||
int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock){
|
||||
int dsp5680xx_f_wr(struct target *t, uint8_t *b, uint32_t a, uint32_t count, int is_flash_lock)
|
||||
{
|
||||
struct target *target = t;
|
||||
uint32_t address = a;
|
||||
uint8_t *buffer = b;
|
||||
int retval = ERROR_OK;
|
||||
if (dsp5680xx_target_status(target,NULL,NULL) != TARGET_HALTED){
|
||||
if (!dsp5680xx_context.debug_mode_enabled) {
|
||||
retval = eonce_enter_debug_mode(target, NULL);
|
||||
err_check_propagate(retval);
|
||||
}
|
||||
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
||||
// Download the pgm that flashes.
|
||||
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
||||
uint32_t my_favourite_ram_address = 0x8700; // This seems to be a safe address. This one is the one used by codewarrior in 56801x_flash.cfg
|
||||
const uint32_t len = pgm_write_pflash_length;
|
||||
uint32_t ram_addr = 0x8700;
|
||||
/**
|
||||
* This seems to be a safe address.
|
||||
* This one is the one used by codewarrior in 56801x_flash.cfg
|
||||
*/
|
||||
if (!is_flash_lock) {
|
||||
retval = dsp5680xx_write(target, my_favourite_ram_address, 1, pgm_write_pflash_length*2,(uint8_t *) pgm_write_pflash);
|
||||
retval = dsp5680xx_write(target, ram_addr, 1, len*2, (uint8_t *) pgm_write_pflash);
|
||||
err_check_propagate(retval);
|
||||
retval = dsp5680xx_execute_queue();
|
||||
err_check_propagate(retval);
|
||||
|
|
@ -1584,7 +1693,7 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
|
|||
retval = core_move_value_at_r2_disp(target,0x00,HFM_PROTB);// write to HMF_PROTB, clear protection
|
||||
err_check_propagate(retval);
|
||||
if (count%2) {
|
||||
//TODO implement handling of odd number of words.
|
||||
/* TODO implement handling of odd number of words. */
|
||||
retval = ERROR_FAIL;
|
||||
const char *msg = "Cannot handle odd number of words.";
|
||||
err_check(retval, DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT, msg);
|
||||
|
|
@ -1599,7 +1708,7 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
|
|||
retval = core_tx_upper_data(target, tmp, &drscan_data);
|
||||
err_check_propagate(retval);
|
||||
|
||||
retval = dsp5680xx_resume(target,0,my_favourite_ram_address,0,0);
|
||||
retval = dsp5680xx_resume(target, 0, ram_addr, 0, 0);
|
||||
err_check_propagate(retval);
|
||||
|
||||
int counter = FLUSH_COUNT_FLASH;
|
||||
|
|
@ -1620,9 +1729,10 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
|
|||
}
|
||||
dsp5680xx_context.flush = 1;
|
||||
if (!is_flash_lock) {
|
||||
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
||||
// Verify flash (skip when exec lock sequence)
|
||||
// -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
||||
/** -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
||||
* Verify flash (skip when exec lock sequence)
|
||||
* -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
|
||||
*/
|
||||
uint16_t signature;
|
||||
uint16_t pc_crc;
|
||||
retval = dsp5680xx_f_signature(target, address, i, &signature);
|
||||
|
|
@ -1637,13 +1747,12 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
|
|||
return retval;
|
||||
}
|
||||
|
||||
int dsp5680xx_f_unlock(struct target * target){
|
||||
int dsp5680xx_f_unlock(struct target *target)
|
||||
{
|
||||
int retval = ERROR_OK;
|
||||
uint16_t eonce_status;
|
||||
uint32_t instr;
|
||||
uint32_t ir_out;
|
||||
uint16_t instr_16;
|
||||
uint16_t read_16;
|
||||
struct jtag_tap * tap_chp;
|
||||
struct jtag_tap * tap_cpu;
|
||||
tap_chp = jtag_tap_by_string("dsp568013.chp");
|
||||
|
|
@ -1657,10 +1766,9 @@ int dsp5680xx_f_unlock(struct target * target){
|
|||
err_check(retval, DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE, "Failed to get master tap.");
|
||||
}
|
||||
|
||||
retval = eonce_enter_debug_mode(target,&eonce_status);
|
||||
if(retval == ERROR_OK){
|
||||
retval = eonce_enter_debug_mode_without_reset(target, &eonce_status);
|
||||
if (retval == ERROR_OK)
|
||||
LOG_WARNING("Memory was not locked.");
|
||||
}
|
||||
|
||||
jtag_add_reset(0,1);
|
||||
jtag_add_sleep(TIME_DIV_FREESCALE*200*1000);
|
||||
|
|
@ -1717,28 +1825,16 @@ int dsp5680xx_f_unlock(struct target * target){
|
|||
|
||||
tap_cpu->enabled = true;
|
||||
tap_chp->enabled = false;
|
||||
|
||||
instr = JTAG_INSTR_ENABLE_ONCE;
|
||||
//Two rounds of jtag 0x6 (enable eonce) to enable EOnCE.
|
||||
retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
|
||||
err_check_propagate(retval);
|
||||
instr = JTAG_INSTR_DEBUG_REQUEST;
|
||||
retval = dsp5680xx_irscan(target, & instr, & ir_out,DSP5680XX_JTAG_CORE_TAP_IRLEN);
|
||||
err_check_propagate(retval);
|
||||
instr_16 = 0x1;
|
||||
retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
|
||||
err_check_propagate(retval);
|
||||
instr_16 = 0x20;
|
||||
retval = dsp5680xx_drscan(target,(uint8_t *) & instr_16,(uint8_t *) & read_16,8);
|
||||
err_check_propagate(retval);
|
||||
jtag_add_sleep(TIME_DIV_FREESCALE*100*1000);
|
||||
jtag_add_reset(0,0);
|
||||
jtag_add_sleep(TIME_DIV_FREESCALE*300*1000);
|
||||
target->state = TARGET_RUNNING;
|
||||
dsp5680xx_context.debug_mode_enabled = false;
|
||||
return retval;
|
||||
}
|
||||
|
||||
int dsp5680xx_f_lock(struct target * target){
|
||||
int dsp5680xx_f_lock(struct target *target)
|
||||
{
|
||||
int retval;
|
||||
struct jtag_tap *tap_chp;
|
||||
struct jtag_tap *tap_cpu;
|
||||
uint16_t lock_word[] = {HFM_LOCK_FLASH};
|
||||
retval = dsp5680xx_f_wr(target,(uint8_t *)(lock_word),HFM_LOCK_ADDR_L,2,1);
|
||||
err_check_propagate(retval);
|
||||
|
|
@ -1752,6 +1848,21 @@ int dsp5680xx_f_lock(struct target * target){
|
|||
jtag_add_reset(0,0);
|
||||
jtag_add_sleep(TIME_DIV_FREESCALE*300*1000);
|
||||
|
||||
tap_chp = jtag_tap_by_string("dsp568013.chp");
|
||||
if (tap_chp == NULL) {
|
||||
retval = ERROR_FAIL;
|
||||
err_check(retval, DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER, "Failed to get master tap.");
|
||||
}
|
||||
tap_cpu = jtag_tap_by_string("dsp568013.cpu");
|
||||
if (tap_cpu == NULL) {
|
||||
retval = ERROR_FAIL;
|
||||
err_check(retval, DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE, "Failed to get master tap.");
|
||||
}
|
||||
target->state = TARGET_RUNNING;
|
||||
dsp5680xx_context.debug_mode_enabled = false;
|
||||
tap_cpu->enabled = false;
|
||||
tap_chp->enabled = true;
|
||||
retval = switch_tap(target, tap_chp, tap_cpu);
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -256,6 +256,7 @@ struct dsp5680xx_common{
|
|||
//TODO
|
||||
uint32_t stored_pc;
|
||||
int flush;
|
||||
bool debug_mode_enabled;
|
||||
};
|
||||
|
||||
extern struct dsp5680xx_common dsp5680xx_context;
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user