Rick Altherr <kc8apf@kc8apf.net> switch to new syntax for target events
git-svn-id: svn://svn.berlios.de/openocd/trunk@1116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
be968a5400
commit
e4218ebb8f
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@ -20,24 +20,23 @@ noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7t
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etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
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nobase_dist_pkglib_DATA = xscale/debug_handler.bin target/at91eb40a.cfg \
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event/at91r40008_reset.script event/sam7x256_reset.script \
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target/at91r40008.cfg target/lpc2148.cfg target/lpc2148_rclk.cfg target/lpc2148_2mhz.cfg target/lpc2294.cfg \
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target/sam7x256.cfg target/str710.cfg target/str912.cfg target/nslu2.cfg target/pxa255_sst.cfg \
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target/pxa255.cfg target/zy1000.cfg event/at91sam9260_reset.script target/at91sam9260.cfg \
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target/wi-9c.cfg event/wi-9c_reset.script event/pxa255_reset.script target/stm32.cfg target/xba_revA3.cfg event/xba_revA3.script \
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target/pxa255.cfg target/zy1000.cfg target/at91sam9260.cfg \
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target/wi-9c.cfg target/stm32.cfg target/xba_revA3.cfg \
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ecos/at91eb40a.elf target/lm3s6965.cfg interface/parport.cfg \
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event/omap5912_reset.script interface/jtagkey-tiny.cfg interface/jtagkey.cfg interface/str9-comstick.cfg \
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interface/jtagkey-tiny.cfg interface/jtagkey.cfg interface/str9-comstick.cfg \
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target/epc9301.cfg target/ipx42x.cfg target/lpc2129.cfg target/netx500.cfg \
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target/omap5912.cfg target/pxa270.cfg target/str750.cfg target/str9comstick.cfg \
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target/str730.cfg target/stm32stick.cfg event/str710_program.script \
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target/str730.cfg target/stm32stick.cfg \
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target/lm3s811.cfg interface/luminary.cfg interface/luminary-libftdi.cfg interface/luminary-lm3s811.cfg \
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target/imx31.cfg target/lm3s3748.cfg \
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interface/stm32-stick.cfg interface/calao-usb-a9260-c01.cfg interface/calao-usb-a9260-c02.cfg \
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interface/calao-usb-a9260.cfg target/at91sam9260minimal.cfg \
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interface/chameleon.cfg interface/at91rm9200.cfg interface/jlink.cfg interface/arm-usb-ocd.cfg \
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interface/signalyzer.cfg event/eir-sam7se512_reset.script target/eir-sam7se512.cfg \
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event/hammer_reset.script interface/flyswatter.cfg target/hammer.cfg \
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event/str730_program.script event/str750_program.script interface/olimex-jtag-tiny-a.cfg \
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interface/signalyzer.cfg target/eir-sam7se512.cfg \
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interface/flyswatter.cfg target/hammer.cfg \
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interface/olimex-jtag-tiny-a.cfg \
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target/pic32mx.cfg target/aduc702x.cfg interface/dummy.cfg interface/olimex-arm-usb-ocd.cfg target/s3c2440.cfg \
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interface/openocd-usb.cfg target/test_syntax_error.cfg target/test_reset_syntax_error.cfg
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@ -1,7 +0,0 @@
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wait_halt
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sleep 10
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poll
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# Ethernut 3 remapping is required to access external flash memory.
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mww 0xffe00000 0x1000213d
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mww 0xffe00004 0x20003e3d
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mww 0xffe00020 0x00000001
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@ -1,58 +0,0 @@
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mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
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mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
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mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
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sleep 10 # wait 10 ms
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mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
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sleep 20 # wait 20 ms
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mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
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sleep 10 # wait 10 ms
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mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
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sleep 10 # wait 10 ms
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jtag_speed 0 # Increase JTAG Speed to 6 MHz
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arm7_9 dcc_downloads enable # Enable faster DCC downloads
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mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
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mww 0xffffec04 0x09070806 # SMC_PULSE0
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mww 0xffffec08 0x000d000b # SMC_CYCLE0
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mww 0xffffec0c 0x00001003 # SMC_MODE0
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flash probe 0 # Identify flash bank 0
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mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
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mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
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mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
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#mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
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mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
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mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
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mww 0x20000000 0
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mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
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mww 0x20000000 0
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mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x4
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mww 0x20000000 0
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mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
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mww 0x20000000 0
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mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
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mww 0x20000000 0
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mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
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@ -1,87 +0,0 @@
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# WDT_MR, disable watchdog
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mww 0xFFFFFD44 0x00008000
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# RSTC_MR, enable user reset
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mww 0xfffffd08 0xa5000001
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# CKGR_MOR
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mww 0xFFFFFC20 0x00000601
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sleep 10
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# CKGR_PLLR
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mww 0xFFFFFC2C 0x00481c0e
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sleep 10
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# PMC_MCKR
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mww 0xFFFFFC30 0x00000007
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sleep 10
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# PMC_IER
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mww 0xFFFFFF60 0x00480100
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#
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# Enable SDRAM interface.
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#
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# Enable SDRAM control at PIO A.
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mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
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mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
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# Enable address bus (A0, A2-A11, A13-A17) at PIO B
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mww 0xfffff674 0x0003effd # PIO_BSR_OFF
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mww 0xfffff604 0x0003effd # PIO_PDR_OFF
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# Enable 16 bit data bus at PIO C
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mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
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mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
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# Enable SDRAM chip select
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mww 0xffffff80 0x00000002 # EBI_CSA_OFF
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# Set SDRAM characteristics in configuration register.
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# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
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mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
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sleep 10
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# Issue 16 bit SDRAM command: NOP
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mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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# Issue 16 bit SDRAM command: Precharge all
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mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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# Issue 8 auto-refresh cycles
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mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000000
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# Issue 16 bit SDRAM command: Set mode register
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mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
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mww 0x20000014 0xcafedede
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# Set refresh rate count ???
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mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
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# Issue 16 bit SDRAM command: Normal mode
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mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
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mww 0x20000000 0x00000180
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#
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# Enable external reset key.
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#
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mww 0xfffffd08 0xa5000001
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@ -1,24 +0,0 @@
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# Reset Script for the TinCanTools S3C2410 Based Hammer Module
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# http://www.tincantools.com
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#
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# Setup primary clocks and initialize the SDRAM
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mww 0x53000000 0x00000000
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mww 0x4a000008 0xffffffff
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mww 0x4a00000c 0x000007ff
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mww 0x4c000000 0x00ffffff
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mww 0x4c000014 0x00000003
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mww 0x4c000004 0x000a1031
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mww 0x48000000 0x11111122
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mww 0x48000004 0x00000700
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mww 0x48000008 0x00000700
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mww 0x4800000c 0x00000700
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mww 0x48000010 0x00000700
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mww 0x48000014 0x00000700
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mww 0x48000018 0x00000700
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mww 0x4800001c 0x00018005
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mww 0x48000020 0x00018005
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mww 0x48000024 0x009c0459
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mww 0x48000028 0x000000b2
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mww 0x4800002c 0x00000030
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mww 0x48000030 0x00000030
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flash probe 0
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@ -1,21 +0,0 @@
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#
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# halt target
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#
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poll
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sleep 1
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halt
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wait_halt
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#
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# disable wdt
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#
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mww 0xfffec808 0x000000f5
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mww 0xfffec808 0x000000a0
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mww 0xfffeb048 0x0000aaaa
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sleep 500
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mww 0xfffeb048 0x00005555
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sleep 500
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#
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# detect flash
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#
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flash probe 0
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@ -1,74 +0,0 @@
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#configuration file for PXA250 Evaluation Board
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# -----------------------------------------------------
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#
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xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
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#
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# setup GPIO
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#
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mww 0x40E00018 0x00008000 #CPSR0
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sleep 20
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mww 0x40E0001C 0x00000002 #GPSR1
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sleep 20
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mww 0x40E00020 0x00000008 #GPSR2
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sleep 20
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mww 0x40E0000C 0x00008000 #GPDR0
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sleep 20
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mww 0x40E00054 0x80000000 #GAFR0_L
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sleep 20
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mww 0x40E00058 0x00188010 #GAFR0_H
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sleep 20
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mww 0x40E0005C 0x60908018 #GAFR1_L
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sleep 20
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mww 0x40E0000C 0x0280E000 #GPDR0
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sleep 20
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mww 0x40E00010 0x821C88B2 #GPDR1
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sleep 20
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mww 0x40E00014 0x000F03DB #GPDR2
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sleep 20
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mww 0x40E00000 0x000F03DB #GPLR0
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sleep 20
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mww 0x40F00004 0x00000020 #PSSR
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sleep 20
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#
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# setup memory controller
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#
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mww 0x48000008 0x01111998 #MSC0
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sleep 20
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mww 0x48000010 0x00047ff0 #MSC2
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sleep 20
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mww 0x48000014 0x00000000 #MECR
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sleep 20
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mww 0x48000028 0x00010504 #MCMEM0
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sleep 20
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mww 0x4800002C 0x00010504 #MCMEM1
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sleep 20
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mww 0x48000030 0x00010504 #MCATT0
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sleep 20
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mww 0x48000034 0x00010504 #MCATT1
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sleep 20
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mww 0x48000038 0x00004715 #MCIO0
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sleep 20
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mww 0x4800003C 0x00004715 #MCIO1
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sleep 20
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#
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mww 0x48000004 0x03CA4018 #MDREF
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sleep 20
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mww 0x48000004 0x004B4018 #MDREF
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sleep 20
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mww 0x48000004 0x000B4018 #MDREF
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sleep 20
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mww 0x48000004 0x000BC018 #MDREF
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sleep 20
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mww 0x48000000 0x00001AC8 #MDCNFG
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sleep 20
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sleep 20
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mww 0x48000000 0x00001AC9 #MDCNFG
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sleep 20
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mww 0x48000040 0x00000000 #MDMRS
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sleep 20
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@ -1,23 +0,0 @@
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#
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# Init - taken form the script openocd_at91sam7_ecr.script
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#
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# I take this script from the following page:
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#
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# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html
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#
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# disable watchdog
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mww 0xfffffd44 0x00008000
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# enable user reset
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mww 0xfffffd08 0xa5000001
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# CKGR_MOR : enable the main oscillator
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mww 0xfffffc20 0x00000601
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sleep 10
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# CKGR_PLLR: 96.1097 MHz
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mww 0xfffffc2c 0x00481c0e
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sleep 10
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# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
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mww 0xfffffc30 0x00000007
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sleep 10
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# MC_FMR: flash mode (FWS=1,FMCN=60)
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mww 0xffffff60 0x003c0100
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sleep 100
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@ -1,2 +0,0 @@
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flash protect 0 0 7 off
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flash protect 1 0 1 off
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@ -1 +0,0 @@
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flash protect 0 0 7 off
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@ -1,2 +0,0 @@
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flash protect 0 0 7 off
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flash protect 1 0 1 off
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@ -1,70 +0,0 @@
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mww 0x90600104 0x33313333
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mww 0xA0700000 0x00000001 # Enable the memory controller.
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mww 0xA0700024 0x00000006 # Set the refresh counter 6
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mww 0xA0700028 0x00000001 #
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mww 0xA0700030 0x00000001 # Set the precharge period
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mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
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mww 0xA070003C 0x00000001 # tAPR
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mww 0xA0700040 0x00000005 # tDAL
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mww 0xA0700044 0x00000001 # tWR
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mww 0xA0700048 0x00000006 # tRC 32 clock cycles
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mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
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mww 0xA0700054 0x00000001 # tRRD
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mww 0xA0700058 0x00000001 # tMRD
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mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
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mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
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mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
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mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
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#
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mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
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#
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mww 0xA0700020 0x00000103 # issue SDRAM PALL command
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#
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mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
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#
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# Add some dummy writes to give the SDRAM time to settle, it needs two
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# AHB clock cycles, here we poke in the debugger flag, this lets
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# the software know that we are in the debugger
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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#
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
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#
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mww 0xA0700024 0x00000030 # Set the refresh counter to 30
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mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
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#
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# Next we perform a read of RAM.
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# mw = move word.
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mdw 0x00022000
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# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
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#
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mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
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mww 0xA0700100 0x00084280 # Enable buffer access
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mww 0xA0700120 0x00084280 # Enable buffer access
|
||||
mww 0xA0700140 0x00084280 # Enable buffer access
|
||||
mww 0xA0700160 0x00084280 # Enable buffer access
|
||||
|
||||
#Set byte lane state (static mem 1)"
|
||||
mww 0xA0700220, 0x00000082
|
||||
#Flash Start
|
||||
mww 0xA09001F8, 0x50000000
|
||||
#Flash Mask Reg
|
||||
mww 0xA09001FC, 0xFF000001
|
||||
mww 0xA0700028, 0x00000001
|
||||
|
||||
# RAMAddr = 0x00020000
|
||||
# RAMSize = 0x00004000
|
||||
|
||||
# Set the processor mode
|
||||
reg cpsr 0xd3
|
||||
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
|
||||
#############################################################################
|
||||
# setup expansion bus CS, disable external wdt
|
||||
#############################################################################
|
||||
mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000
|
||||
mww 0xc4000004 0x94d10013 #CS1
|
||||
mww 0xc4000008 0x95960003 #CS2
|
||||
mww 0xc400000c 0x00000000 #CS3
|
||||
mww 0xc4000010 0x80900003 #CS4
|
||||
mww 0xc4000014 0x9d520003 #CS5
|
||||
mww 0xc4000018 0x81860001 #CS6
|
||||
mww 0xc400001c 0x80900003 #CS7
|
||||
|
||||
#############################################################################
|
||||
# init SDRAM controller: 16MB, one bank, CL3
|
||||
#############################################################################
|
||||
mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3
|
||||
mww 0xCC000004 0 # disable refresh
|
||||
mww 0xCC000008 3 # NOP
|
||||
sleep 100
|
||||
mww 0xCC000004 2100 # set refresh counter
|
||||
mww 0xCC000008 2 # Precharge All Banks
|
||||
sleep 100
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 1 # Mode Select CL3
|
||||
|
||||
#mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash
|
||||
#mirror at 0x00000000
|
||||
|
||||
#big endian
|
||||
reg XSCALE_CTRL 0xF8
|
||||
|
||||
#
|
||||
# detect flash
|
||||
#
|
||||
flash probe 0
|
||||
|
|
@ -11,7 +11,15 @@ jtag_device 4 0x1 0xf 0xe
|
|||
target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
|
||||
|
||||
|
||||
[new_target_name] configure -event old-gdb_program_config { script event/at91r40008_reset.script }
|
||||
[new_target_name] configure -event gdb-flash-erase-start {
|
||||
wait_halt
|
||||
sleep 10
|
||||
poll
|
||||
# Ethernut 3 remapping is required to access external flash memory.
|
||||
mww 0xffe00000 0x1000213d
|
||||
mww 0xffe00004 0x20003e3d
|
||||
mww 0xffe00020 0x00000001
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,65 @@ jtag_ntrst_delay 0
|
|||
|
||||
target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs
|
||||
|
||||
[new_target_name] configure -event reset-init { script event/at91sam9260_reset.script }
|
||||
[new_target_name] configure -event reset-init {
|
||||
mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
|
||||
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
|
||||
|
||||
mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
|
||||
sleep 20 # wait 20 ms
|
||||
mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
|
||||
sleep 10 # wait 10 ms
|
||||
mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
|
||||
sleep 20 # wait 20 ms
|
||||
mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
|
||||
sleep 10 # wait 10 ms
|
||||
mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
|
||||
sleep 10 # wait 10 ms
|
||||
|
||||
jtag_speed 0 # Increase JTAG Speed to 6 MHz
|
||||
arm7_9 dcc_downloads enable # Enable faster DCC downloads
|
||||
|
||||
mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
|
||||
mww 0xffffec04 0x09070806 # SMC_PULSE0
|
||||
mww 0xffffec08 0x000d000b # SMC_CYCLE0
|
||||
mww 0xffffec0c 0x00001003 # SMC_MODE0
|
||||
|
||||
flash probe 0 # Identify flash bank 0
|
||||
|
||||
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
|
||||
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
|
||||
|
||||
mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
|
||||
|
||||
#mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
|
||||
mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
|
||||
|
||||
mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x4
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
|
||||
mww 0x20000000 0
|
||||
mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,94 @@ jtag_device 4 0x1 0xf 0xe
|
|||
target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
|
||||
|
||||
|
||||
[new_target_name] configure -event reset-init { script event/eir-sam7se512_reset.script }
|
||||
[new_target_name] configure -event reset-init {
|
||||
# WDT_MR, disable watchdog
|
||||
mww 0xFFFFFD44 0x00008000
|
||||
|
||||
# RSTC_MR, enable user reset
|
||||
mww 0xfffffd08 0xa5000001
|
||||
|
||||
# CKGR_MOR
|
||||
mww 0xFFFFFC20 0x00000601
|
||||
sleep 10
|
||||
|
||||
# CKGR_PLLR
|
||||
mww 0xFFFFFC2C 0x00481c0e
|
||||
sleep 10
|
||||
|
||||
# PMC_MCKR
|
||||
mww 0xFFFFFC30 0x00000007
|
||||
sleep 10
|
||||
|
||||
# PMC_IER
|
||||
mww 0xFFFFFF60 0x00480100
|
||||
|
||||
#
|
||||
# Enable SDRAM interface.
|
||||
#
|
||||
|
||||
# Enable SDRAM control at PIO A.
|
||||
mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
|
||||
mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
|
||||
|
||||
# Enable address bus (A0, A2-A11, A13-A17) at PIO B
|
||||
mww 0xfffff674 0x0003effd # PIO_BSR_OFF
|
||||
mww 0xfffff604 0x0003effd # PIO_PDR_OFF
|
||||
|
||||
# Enable 16 bit data bus at PIO C
|
||||
mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
|
||||
mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
|
||||
|
||||
# Enable SDRAM chip select
|
||||
mww 0xffffff80 0x00000002 # EBI_CSA_OFF
|
||||
|
||||
# Set SDRAM characteristics in configuration register.
|
||||
# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
|
||||
mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
|
||||
sleep 10
|
||||
|
||||
# Issue 16 bit SDRAM command: NOP
|
||||
mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
|
||||
# Issue 16 bit SDRAM command: Precharge all
|
||||
mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
|
||||
# Issue 8 auto-refresh cycles
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
|
||||
# Issue 16 bit SDRAM command: Set mode register
|
||||
mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
|
||||
mww 0x20000014 0xcafedede
|
||||
|
||||
# Set refresh rate count ???
|
||||
mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
|
||||
|
||||
# Issue 16 bit SDRAM command: Normal mode
|
||||
mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000180
|
||||
|
||||
#
|
||||
# Enable external reset key.
|
||||
#
|
||||
mww 0xfffffd08 0xa5000001
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,32 @@ jtag_device 4 0x1 0xf 0xe
|
|||
|
||||
target create target0 arm920t -endian little -chain-position 0 -variant arm920t
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40800000 -work-area-size 0x20000 -work-area-backup 0
|
||||
[new_target_name] configure -event reset-init { script event/hammer_reset.script }
|
||||
[new_target_name] configure -event reset-init {
|
||||
# Reset Script for the TinCanTools S3C2410 Based Hammer Module
|
||||
# http://www.tincantools.com
|
||||
#
|
||||
# Setup primary clocks and initialize the SDRAM
|
||||
mww 0x53000000 0x00000000
|
||||
mww 0x4a000008 0xffffffff
|
||||
mww 0x4a00000c 0x000007ff
|
||||
mww 0x4c000000 0x00ffffff
|
||||
mww 0x4c000014 0x00000003
|
||||
mww 0x4c000004 0x000a1031
|
||||
mww 0x48000000 0x11111122
|
||||
mww 0x48000004 0x00000700
|
||||
mww 0x48000008 0x00000700
|
||||
mww 0x4800000c 0x00000700
|
||||
mww 0x48000010 0x00000700
|
||||
mww 0x48000014 0x00000700
|
||||
mww 0x48000018 0x00000700
|
||||
mww 0x4800001c 0x00018005
|
||||
mww 0x48000020 0x00018005
|
||||
mww 0x48000024 0x009c0459
|
||||
mww 0x48000028 0x000000b2
|
||||
mww 0x4800002c 0x00000030
|
||||
mww 0x48000030 0x00000030
|
||||
flash probe 0
|
||||
}
|
||||
|
||||
# speed up memory downloads
|
||||
arm7 fast_memory_access enable
|
||||
|
|
|
|||
|
|
@ -11,7 +11,29 @@ jtag_device 4 0x1 0x0 0xe
|
|||
jtag_device 8 0x0 0x0 0x0
|
||||
|
||||
target create target0 arm926ejs -endian little -chain-position 1 -variant arm926ejs
|
||||
[new_target_name] configure -event reset-init { script event/omap5912_reset.script }
|
||||
[new_target_name] configure -event reset-init {
|
||||
#
|
||||
# halt target
|
||||
#
|
||||
poll
|
||||
sleep 1
|
||||
halt
|
||||
wait_halt
|
||||
#
|
||||
# disable wdt
|
||||
#
|
||||
mww 0xfffec808 0x000000f5
|
||||
mww 0xfffec808 0x000000a0
|
||||
|
||||
mww 0xfffeb048 0x0000aaaa
|
||||
sleep 500
|
||||
mww 0xfffeb048 0x00005555
|
||||
sleep 500
|
||||
#
|
||||
# detect flash
|
||||
#
|
||||
flash probe 0
|
||||
}
|
||||
|
||||
# omap5912 lcd frame buffer as working area
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0
|
||||
|
|
|
|||
|
|
@ -3,7 +3,78 @@ jtag_nsrst_delay 200
|
|||
jtag_ntrst_delay 200
|
||||
|
||||
target create target0 xscale -endian little -chain-position 0 -variant pxa255
|
||||
[new_target_name] configure -event reset-init { script event/pxa255_reset.script }
|
||||
[new_target_name] configure -event reset-init {
|
||||
xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
|
||||
#
|
||||
# setup GPIO
|
||||
#
|
||||
mww 0x40E00018 0x00008000 #CPSR0
|
||||
sleep 20
|
||||
mww 0x40E0001C 0x00000002 #GPSR1
|
||||
sleep 20
|
||||
mww 0x40E00020 0x00000008 #GPSR2
|
||||
sleep 20
|
||||
mww 0x40E0000C 0x00008000 #GPDR0
|
||||
sleep 20
|
||||
mww 0x40E00054 0x80000000 #GAFR0_L
|
||||
sleep 20
|
||||
mww 0x40E00058 0x00188010 #GAFR0_H
|
||||
sleep 20
|
||||
mww 0x40E0005C 0x60908018 #GAFR1_L
|
||||
sleep 20
|
||||
mww 0x40E0000C 0x0280E000 #GPDR0
|
||||
sleep 20
|
||||
mww 0x40E00010 0x821C88B2 #GPDR1
|
||||
sleep 20
|
||||
mww 0x40E00014 0x000F03DB #GPDR2
|
||||
sleep 20
|
||||
mww 0x40E00000 0x000F03DB #GPLR0
|
||||
sleep 20
|
||||
|
||||
|
||||
mww 0x40F00004 0x00000020 #PSSR
|
||||
sleep 20
|
||||
|
||||
#
|
||||
# setup memory controller
|
||||
#
|
||||
mww 0x48000008 0x01111998 #MSC0
|
||||
sleep 20
|
||||
mww 0x48000010 0x00047ff0 #MSC2
|
||||
sleep 20
|
||||
mww 0x48000014 0x00000000 #MECR
|
||||
sleep 20
|
||||
mww 0x48000028 0x00010504 #MCMEM0
|
||||
sleep 20
|
||||
mww 0x4800002C 0x00010504 #MCMEM1
|
||||
sleep 20
|
||||
mww 0x48000030 0x00010504 #MCATT0
|
||||
sleep 20
|
||||
mww 0x48000034 0x00010504 #MCATT1
|
||||
sleep 20
|
||||
mww 0x48000038 0x00004715 #MCIO0
|
||||
sleep 20
|
||||
mww 0x4800003C 0x00004715 #MCIO1
|
||||
sleep 20
|
||||
#
|
||||
mww 0x48000004 0x03CA4018 #MDREF
|
||||
sleep 20
|
||||
mww 0x48000004 0x004B4018 #MDREF
|
||||
sleep 20
|
||||
mww 0x48000004 0x000B4018 #MDREF
|
||||
sleep 20
|
||||
mww 0x48000004 0x000BC018 #MDREF
|
||||
sleep 20
|
||||
mww 0x48000000 0x00001AC8 #MDCNFG
|
||||
sleep 20
|
||||
|
||||
sleep 20
|
||||
|
||||
mww 0x48000000 0x00001AC9 #MDCNFG
|
||||
sleep 20
|
||||
mww 0x48000040 0x00000000 #MDMRS
|
||||
sleep 20
|
||||
}
|
||||
|
||||
reset_config trst_and_srst
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,24 @@ reset_config srst_only srst_pulls_trst
|
|||
jtag_device 4 0x1 0xf 0xe
|
||||
|
||||
target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
|
||||
[new_target_name] configure -event reset-init { script event/sam7x256_reset.script }
|
||||
[new_target_name] configure -event reset-init {
|
||||
# disable watchdog
|
||||
mww 0xfffffd44 0x00008000
|
||||
# enable user reset
|
||||
mww 0xfffffd08 0xa5000001
|
||||
# CKGR_MOR : enable the main oscillator
|
||||
mww 0xfffffc20 0x00000601
|
||||
sleep 10
|
||||
# CKGR_PLLR: 96.1097 MHz
|
||||
mww 0xfffffc2c 0x00481c0e
|
||||
sleep 10
|
||||
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
|
||||
mww 0xfffffc30 0x00000007
|
||||
sleep 10
|
||||
# MC_FMR: flash mode (FWS=1,FMCN=60)
|
||||
mww 0xffffff60 0x003c0100
|
||||
sleep 100
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,11 @@ jtag_device 4 0x1 0xf 0xe
|
|||
target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
|
||||
[new_target_name] configure -event reset-start { jtag_khz 10 }
|
||||
[new_target_name] configure -event reset-init { jtag_khz 6000 }
|
||||
[new_target_name] configure -event old-gdb_program_config { script event/str710_program.script }
|
||||
[new_target_name] configure -event gdb-flash-erase-start {
|
||||
flash protect 0 0 7 off
|
||||
flash protect 1 0 1 off
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
#flash bank str7x <base> <size> 0 0 <target#> <variant>
|
||||
|
|
|
|||
|
|
@ -19,7 +19,10 @@ jtag_ntrst_delay 500
|
|||
target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
|
||||
[new_target_name] configure -event reset-start { jtag_khz 10 }
|
||||
[new_target_name] configure -event reset-init { jtag_khz 3000 }
|
||||
[new_target_name] configure -event old-gdb_program_config { script event/str730_program.script }
|
||||
[new_target_name] configure -event gdb-¿ash-erase-start {
|
||||
flash protect 0 0 7 off
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
#flash bank <driver> <base> <size> <chip_width> <bus_width>
|
||||
|
|
|
|||
|
|
@ -20,7 +20,11 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm
|
|||
|
||||
[new_target_name] configure -event reset-start { jtag_khz 10 }
|
||||
[new_target_name] configure -event reset-init { jtag_khz 3000 }
|
||||
[new_target_name] configure -event old-gdb_program_config { script event/str750_program.script }
|
||||
[new_target_name] configure -event gdb-¿ash-erase-start {
|
||||
flash protect 0 0 7 off
|
||||
flash protect 1 0 1 off
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
|
||||
|
||||
#flash bank <driver> <base> <size> <chip_width> <bus_width>
|
||||
|
|
|
|||
|
|
@ -15,7 +15,78 @@ jtag_ntrst_delay 0
|
|||
######################
|
||||
|
||||
target create target0 arm926ejs -endian big -chain-position 0 -variant arm926ejs
|
||||
[new_target_name] configure -event reset-init { script event/wi-9c_reset.script }
|
||||
[new_target_name] configure -event reset-init {
|
||||
mww 0x90600104 0x33313333
|
||||
mww 0xA0700000 0x00000001 # Enable the memory controller.
|
||||
mww 0xA0700024 0x00000006 # Set the refresh counter 6
|
||||
mww 0xA0700028 0x00000001 #
|
||||
mww 0xA0700030 0x00000001 # Set the precharge period
|
||||
mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
|
||||
mww 0xA070003C 0x00000001 # tAPR
|
||||
mww 0xA0700040 0x00000005 # tDAL
|
||||
mww 0xA0700044 0x00000001 # tWR
|
||||
mww 0xA0700048 0x00000006 # tRC 32 clock cycles
|
||||
mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
|
||||
mww 0xA0700054 0x00000001 # tRRD
|
||||
mww 0xA0700058 0x00000001 # tMRD
|
||||
mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
|
||||
mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
|
||||
mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
|
||||
mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
|
||||
#
|
||||
mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
|
||||
mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
|
||||
mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
|
||||
mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
|
||||
#
|
||||
mww 0xA0700020 0x00000103 # issue SDRAM PALL command
|
||||
#
|
||||
mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
|
||||
#
|
||||
# Add some dummy writes to give the SDRAM time to settle, it needs two
|
||||
# AHB clock cycles, here we poke in the debugger flag, this lets
|
||||
# the software know that we are in the debugger
|
||||
mww 0xA0900000 0x00000002
|
||||
mww 0xA0900000 0x00000002
|
||||
mww 0xA0900000 0x00000002
|
||||
mww 0xA0900000 0x00000002
|
||||
mww 0xA0900000 0x00000002
|
||||
#
|
||||
mdw 0xA0900000
|
||||
mdw 0xA0900000
|
||||
mdw 0xA0900000
|
||||
mdw 0xA0900000
|
||||
mdw 0xA0900000
|
||||
#
|
||||
mww 0xA0700024 0x00000030 # Set the refresh counter to 30
|
||||
mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
|
||||
#
|
||||
# Next we perform a read of RAM.
|
||||
# mw = move word.
|
||||
mdw 0x00022000
|
||||
# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
|
||||
#
|
||||
mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
|
||||
mww 0xA0700100 0x00084280 # Enable buffer access
|
||||
mww 0xA0700120 0x00084280 # Enable buffer access
|
||||
mww 0xA0700140 0x00084280 # Enable buffer access
|
||||
mww 0xA0700160 0x00084280 # Enable buffer access
|
||||
|
||||
#Set byte lane state (static mem 1)"
|
||||
mww 0xA0700220, 0x00000082
|
||||
#Flash Start
|
||||
mww 0xA09001F8, 0x50000000
|
||||
#Flash Mask Reg
|
||||
mww 0xA09001FC, 0xFF000001
|
||||
mww 0xA0700028, 0x00000001
|
||||
|
||||
# RAMAddr = 0x00020000
|
||||
# RAMSize = 0x00004000
|
||||
|
||||
# Set the processor mode
|
||||
reg cpsr 0xd3
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
|
||||
|
||||
#####################
|
||||
|
|
|
|||
|
|
@ -10,7 +10,51 @@ jtag_ntrst_delay 100
|
|||
jtag_device 7 0x1 0x7f 0x7e
|
||||
|
||||
target create target0 xscale -endian big -chain-position 0 -variant ixp42x
|
||||
[new_target_name] configure -event reset-init { script event/xba_revA3.script }
|
||||
[new_target_name] configure -event reset-init {
|
||||
#############################################################################
|
||||
# setup expansion bus CS, disable external wdt
|
||||
#############################################################################
|
||||
mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000
|
||||
mww 0xc4000004 0x94d10013 #CS1
|
||||
mww 0xc4000008 0x95960003 #CS2
|
||||
mww 0xc400000c 0x00000000 #CS3
|
||||
mww 0xc4000010 0x80900003 #CS4
|
||||
mww 0xc4000014 0x9d520003 #CS5
|
||||
mww 0xc4000018 0x81860001 #CS6
|
||||
mww 0xc400001c 0x80900003 #CS7
|
||||
|
||||
#############################################################################
|
||||
# init SDRAM controller: 16MB, one bank, CL3
|
||||
#############################################################################
|
||||
mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3
|
||||
mww 0xCC000004 0 # disable refresh
|
||||
mww 0xCC000008 3 # NOP
|
||||
sleep 100
|
||||
mww 0xCC000004 2100 # set refresh counter
|
||||
mww 0xCC000008 2 # Precharge All Banks
|
||||
sleep 100
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 4 # Auto Refresh
|
||||
mww 0xCC000008 1 # Mode Select CL3
|
||||
|
||||
#mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash
|
||||
#mirror at 0x00000000
|
||||
|
||||
#big endian
|
||||
reg XSCALE_CTRL 0xF8
|
||||
|
||||
#
|
||||
# detect flash
|
||||
#
|
||||
flash probe 0
|
||||
}
|
||||
|
||||
[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue