cortex_a: Add support for A15 MPCore
Added Cortex-A15 support for DAP AHB-AP init code as per ADI V5 spec. Also added changes to make the APB MEM-AP to work with A15. Made the the cortex_a target code generic to work with A8, A9 and A15 single core or multicore implementation. Added armv7a code for os_border calculation to work for known A8, A9 and A15 platforms based on the ARM DDI 0344H, ARM DDI 0407F, ARM DDI 0406C ARMV7A architecture docs. Change-Id: Ib2803ab62588bf40f1ae4b9192b619af31525a1a Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1601 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Kamal Dasu
Andreas Fritiofson
parent
806872a34a
commit
e519099ab7
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@ -1339,7 +1339,12 @@ static int dap_rom_display(struct command_context *cmd_ctx,
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type = "Cortex-A9 Debug";
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full = "(Debug Unit)";
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break;
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case 0x4af:
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type = "Cortex-A15 Debug";
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full = "(Debug Unit)";
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break;
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default:
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LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
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type = "-*- unrecognized -*-";
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full = "";
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break;
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@ -1408,9 +1413,9 @@ static int dap_info_command(struct command_context *cmd_ctx,
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command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
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romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
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if (romtable_present) {
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if (romtable_present)
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dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
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} else
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else
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command_print(cmd_ctx, "\tNo ROM table present");
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dap_ap_select(dap, ap_old);
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@ -88,11 +88,50 @@ done:
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/* (void) */ dpm->finish(dpm);
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}
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/* retrieve main id register */
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static int armv7a_read_midr(struct target *target)
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{
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int retval = ERROR_FAIL;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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uint32_t midr;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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/* MRC p15,0,<Rd>,c0,c0,0; read main id register*/
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRC(15, 0, 0, 0, 0, 0),
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&midr);
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if (retval != ERROR_OK)
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goto done;
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armv7a->rev = (midr & 0xf);
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armv7a->partnum = (midr >> 4) & 0xfff;
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armv7a->arch = (midr >> 16) & 0xf;
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armv7a->variant = (midr >> 20) & 0xf;
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armv7a->implementor = (midr >> 24) & 0xff;
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LOG_INFO("%s rev %" PRIx32 ", partnum %" PRIx32 ", arch %" PRIx32
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", variant %" PRIx32 ", implementor %" PRIx32,
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target->cmd_name,
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armv7a->rev,
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armv7a->partnum,
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armv7a->arch,
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armv7a->variant,
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armv7a->implementor);
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done:
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dpm->finish(dpm);
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return retval;
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}
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static int armv7a_read_ttbcr(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct arm_dpm *dpm = armv7a->arm.dpm;
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uint32_t ttbcr;
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uint32_t ttbr0, ttbr1;
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int retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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@ -102,27 +141,55 @@ static int armv7a_read_ttbcr(struct target *target)
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&ttbcr);
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRC(15, 0, 0, 2, 0, 0),
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&ttbr0);
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRC(15, 0, 0, 2, 0, 1),
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&ttbr1);
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if (retval != ERROR_OK)
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goto done;
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LOG_INFO("ttbcr %" PRIx32 "ttbr0 %" PRIx32 "ttbr1 %" PRIx32, ttbcr, ttbr0, ttbr1);
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armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7) != 0) ? 1 : 0;
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armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7)));
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#if 0
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LOG_INFO("ttb1 %s ,ttb0_mask %x",
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armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used",
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armv7a->armv7a_mmu.ttbr0_mask);
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#endif
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if (armv7a->armv7a_mmu.ttbr1_used == 1) {
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LOG_INFO("SVC access above %" PRIx32,
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(uint32_t)(0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
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armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask;
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armv7a->armv7a_mmu.ttbr0_mask = 0;
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retval = armv7a_read_midr(target);
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if (retval != ERROR_OK)
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goto done;
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if (armv7a->partnum & 0xf) {
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/*
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* ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
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* document # ARM DDI 0406C
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*/
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armv7a->armv7a_mmu.ttbr0_mask = 1 << (14 - ((ttbcr & 0x7)));
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} else {
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/* ARM DDI 0344H , ARM DDI 0407F */
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armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 - ((ttbcr & 0x7)));
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/* fix me , default is hard coded LINUX border */
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armv7a->armv7a_mmu.os_border = 0xc0000000;
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}
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LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32,
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armv7a->armv7a_mmu.ttbr1_used ? "used" : "not used",
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armv7a->armv7a_mmu.ttbr0_mask);
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if (armv7a->armv7a_mmu.ttbr1_used == 1) {
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LOG_INFO("SVC access above %" PRIx32,
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(0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
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armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask;
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}
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done:
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dpm->finish(dpm);
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return retval;
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}
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/* method adapted to cortex A : reused arm v4 v5 method*/
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int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
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{
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@ -77,6 +77,7 @@ struct armv7a_cache_common {
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struct armv7a_mmu_common {
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/* following field mmu working way */
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int32_t ttbr0_used;
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int32_t ttbr1_used; /* -1 not initialized, 0 no ttbr1 1 ttbr1 used and */
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uint32_t ttbr0_mask;/* masked to be used */
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uint32_t os_border;
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@ -105,6 +106,11 @@ struct armv7a_common {
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uint8_t cluster_id;
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uint8_t cpu_id;
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bool is_armv7r;
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uint32_t rev;
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uint32_t partnum;
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uint32_t arch;
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uint32_t variant;
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uint32_t implementor;
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/* cache specific to V7 Memory Management Unit compatible with v4_5*/
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struct armv7a_mmu_common armv7a_mmu;
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@ -20,6 +20,9 @@
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* Copyright (C) Broadcom 2012 *
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* ehunter@broadcom.com : Cortex R4 support *
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* *
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* Copyright (C) 2013 Kamal Dasu *
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* kdasu.kdev@gmail.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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@ -164,12 +167,11 @@ static int cortex_a_mmu_modify(struct target *target, int enable)
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/*
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* Cortex-A Basic debug access, very low level assumes state is saved
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*/
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static int cortex_a_init_debug_access(struct target *target)
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static int cortex_a8_init_debug_access(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = armv7a->arm.dap;
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int retval;
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uint32_t dummy;
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LOG_DEBUG(" ");
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@ -185,12 +187,57 @@ static int cortex_a_init_debug_access(struct target *target)
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LOG_USER(
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"Locking debug access failed on first, but succeeded on second try.");
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}
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return retval;
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}
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/*
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* Cortex-A Basic debug access, very low level assumes state is saved
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*/
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static int cortex_a_init_debug_access(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = armv7a->arm.dap;
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int retval;
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uint32_t dbg_osreg;
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uint32_t cortex_part_num;
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struct cortex_a_common *cortex_a = target_to_cortex_a(target);
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LOG_DEBUG(" ");
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cortex_part_num = (cortex_a->cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >>
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CORTEX_A_MIDR_PARTNUM_SHIFT;
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switch (cortex_part_num) {
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case CORTEX_A15_PARTNUM:
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retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
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armv7a->debug_base + CPUDBG_OSLSR,
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&dbg_osreg);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("DBGOSLSR 0x%" PRIx32, dbg_osreg);
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if (dbg_osreg & CPUDBG_OSLAR_LK_MASK)
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/* Unlocking the DEBUG OS registers for modification */
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retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
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armv7a->debug_base + CPUDBG_OSLAR,
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0);
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break;
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case CORTEX_A8_PARTNUM:
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case CORTEX_A9_PARTNUM:
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default:
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retval = cortex_a8_init_debug_access(target);
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}
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if (retval != ERROR_OK)
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return retval;
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/* Clear Sticky Power Down status Bit in PRSR to enable access to
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the registers in the Core Power Domain */
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retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
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armv7a->debug_base + CPUDBG_PRSR, &dummy);
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armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
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LOG_DEBUG("target->coreid %d DBGPRSR 0x%x ", target->coreid, dbg_osreg);
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if (retval != ERROR_OK)
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return retval;
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@ -1799,6 +1846,7 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
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uint32_t dscr;
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uint8_t *tmp_buff = NULL;
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LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx32 " size %" PRIu32 " count%" PRIu32,
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address, size, count);
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if (target->state != TARGET_HALTED) {
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@ -1846,7 +1894,6 @@ static int cortex_a_write_apb_ab_memory(struct target *target,
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/* If end of write is not aligned, or the write is less than 4 bytes */
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if ((end_byte != 0) ||
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((total_u32 == 1) && (total_bytes != 4))) {
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/* Read the last word to avoid corruption during 32 bit write */
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int mem_offset = (total_u32-1) * 4;
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retval = cortex_a_read_apb_ab_memory(target, (address & ~0x3) + mem_offset, 4, 1, &tmp_buff[mem_offset]);
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@ -2163,7 +2210,8 @@ static int cortex_a_read_memory(struct target *target, uint32_t address,
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virt, phys);
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address = phys;
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}
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retval = cortex_a_read_phys_memory(target, address, size, count, buffer);
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retval = cortex_a_read_phys_memory(target, address, size,
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count, buffer);
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} else {
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if (mmu_enabled) {
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retval = cortex_a_check_address(target, address);
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@ -2363,7 +2411,7 @@ static int cortex_a_examine_first(struct target *target)
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struct adiv5_dap *swjdp = armv7a->arm.dap;
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int i;
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int retval = ERROR_OK;
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uint32_t didr, ctypr, ttypr, cpuid;
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uint32_t didr, ctypr, ttypr, cpuid, dbg_osreg;
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/* We do one extra read to ensure DAP is configured,
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* we call ahbap_debugport_init(swjdp) instead
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@ -2447,6 +2495,31 @@ static int cortex_a_examine_first(struct target *target)
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LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
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LOG_DEBUG("didr = 0x%08" PRIx32, didr);
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cortex_a->cpuid = cpuid;
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cortex_a->ctypr = ctypr;
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cortex_a->ttypr = ttypr;
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cortex_a->didr = didr;
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/* Unlocking the debug registers */
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if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
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CORTEX_A15_PARTNUM) {
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retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
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armv7a->debug_base + CPUDBG_OSLAR,
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0);
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if (retval != ERROR_OK)
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return retval;
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}
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retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap,
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armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("target->coreid %d DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
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armv7a->arm.core_type = ARM_MODE_MON;
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retval = cortex_a_dpm_setup(cortex_a, didr);
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if (retval != ERROR_OK)
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@ -33,12 +33,20 @@
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#include "armv7a.h"
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#define CORTEX_A_COMMON_MAGIC 0x411fc082
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#define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
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#define CORTEX_A8_PARTNUM 0xc08
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#define CORTEX_A9_PARTNUM 0xc09
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#define CORTEX_A15_PARTNUM 0xc0f
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#define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
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#define CORTEX_A_MIDR_PARTNUM_SHIFT 4
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#define CPUDBG_CPUID 0xD00
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#define CPUDBG_CTYPR 0xD04
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#define CPUDBG_TTYPR 0xD0C
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#define CPUDBG_LOCKACCESS 0xFB0
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#define CPUDBG_LOCKSTATUS 0xFB4
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#define CPUDBG_OSLAR_LK_MASK (1 << 1)
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#define BRP_NORMAL 0
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#define BRP_CONTEXT 1
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@ -76,6 +84,11 @@ struct cortex_a_common {
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/* Use cortex_a_read_regs_through_mem for fast register reads */
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int fast_reg_read;
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uint32_t cpuid;
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uint32_t ctypr;
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uint32_t ttypr;
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uint32_t didr;
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struct armv7a_common armv7a_common;
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};
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