diff --git a/tcl/target/renesas_rz_five.cfg b/tcl/target/renesas_rz_five.cfg
new file mode 100644
index 000000000..5ab94ab1f
--- /dev/null
+++ b/tcl/target/renesas_rz_five.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Renesas RZ/Five SoC
+#
+# General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz)
+
+transport select jtag
+
+reset_config trst_and_srst srst_gates_jtag
+adapter speed 4000
+adapter srst delay 500
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME r9A07g043u
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME