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cfg: Beaglebone Support

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Added support for the Beaglebone board based on the am335x processor
family.  After much trial and error, I was able to configure the
Icepick-D and connect to the processor, halt execution, and run a sample
program.  This is a unified config file (it doesn't use any include
statements) and further work needs to be done to split out the icepick-d
configuration to be more generic.

Change-Id: Ia1b8e9f01f56bd4f8c575ba3d0160c248583a15e
Signed-off-by: Neil Jensen <neil30al@gmail.com>
Reviewed-on: http://openocd.zylin.com/471
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Neil Jensen 2012-02-18 21:37:08 -06:00 committed by Spencer Oliver
parent 2eb564b756
commit e6580a3cff
1 changed files with 92 additions and 0 deletions
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92
tcl/ti-beaglebone.cfg Normal file
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interface ft2232
#ft2232_device_desc "BeagleBone A"
ft2232_layout xds100v2
ft2232_vid_pid 0x0403 0xa6d0
#jtag_rclk 10
adapter_khz 1000
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME am335x
}
proc icepick_d_tapenable {jrc port} {
# select router
irscan $jrc 7 -endstate IRPAUSE
drscan $jrc 8 0x89 -endstate DRPAUSE
# set ip control
irscan $jrc 2 -endstate IRPAUSE
drscan $jrc 32 [expr 0xa0002108 + ($port << 24)] -endstate DRPAUSE
# for icepick_D
irscan $jrc 2 -endstate IRPAUSE
drscan $jrc 32 0xe0002008 -endstate DRPAUSE
irscan $jrc 0x3F -endstate RUN/IDLE
runtest 10
}
#
# M3 DAP
#
if { [info exists M3_DAP_TAPID] } {
set _M3_DAP_TAPID $M3_DAP_TAPID
} else {
set _M3_DAP_TAPID 0x4b6b902f
}
jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11"
#
# Main DAP
#
if { [info exists DAP_TAPID ] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x4b6b902f
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12"
#
# ICEpick-D (JTAG route controller)
#
if { [info exists JRC_TAPID ] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b94402f
}
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
#
# Cortex A8 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
# SRAM: 64K at 0x4030.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
$_TARGETNAME configure -event reset-assert "am335x_dbginit $_TARGETNAME"
$_TARGETNAME configure -event reset-assert-post "am335x_dbginit $_TARGETNAME"
$_TARGETNAME configure -event gdb-attach {
global _TARGETNAME
am335x_dbginit $_TARGETNAME
echo "Halting target"
halt
}
# Run this to enable invasive debugging. This is run automatically in the
# reset sequence.
proc am335x_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a8 dbginit
}