ARM: new DPM interface
First version of interface for sharing code between ARMv6 and ARMv7a debug modules ... now the architecture includes debug support. (Not the same as for the trimmed-down v7m or v6m though!) This is a first version of an interface that will let the ARM11 and Cortex-A8 support share code, features, and bugfixes. Based on existing code from both of those cores. The ARM v7-AR architecture specification calls this commonality the "Debug Programmer's Model (DPM)", which seemed to be an appropriate acronym -- a TLA even! -- for use in our code. Made it so. :) The initial scope of this just supports register access, and is geared towards supporting top level "struct arm" mechanisms. Later, things like breakpoint and watchpoint support should be included. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
ad75af0b17
commit
e6dc927e97
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@ -75,6 +75,7 @@ ARMV7_SRC = \
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cortex_a8.c
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ARM_DEBUG_SRC = \
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arm_dpm.c \
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arm_jtag.c \
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arm_disassembler.c \
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arm_simulator.c \
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@ -96,6 +97,7 @@ MIPS32_SRC = \
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noinst_HEADERS = \
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algorithm.h \
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arm_dpm.h \
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arm_jtag.h \
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arm_adi_v5.h \
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arm_disassembler.h \
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529
src/target/arm_dpm.c
Normal file
529
src/target/arm_dpm.c
Normal file
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@ -0,0 +1,529 @@
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/*
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* Copyright (C) 2009 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "armv4_5.h" /* REVISIT to become arm.h */
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#include "arm_dpm.h"
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#include "jtag.h"
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#include "register.h"
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/**
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* @file
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* Implements various ARM DPM operations using architectural debug registers.
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* These routines layer over core-specific communication methods to cope with
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* implementation differences between cores like ARM1136 and Cortex-A8.
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*/
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/* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
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* Routines *must* restore the original mode before returning!!
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*/
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static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
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{
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int retval;
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uint32_t cpsr;
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/* restore previous mode */
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if (mode == ARMV4_5_MODE_ANY)
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cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
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/* else force to the specified mode */
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else
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cpsr = mode;
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retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
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/* REVISIT on Cortex-A8, we need a Prefetch Flush operation too ...
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cortex_a8_exec_opcode(target,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
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*/
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return retval;
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}
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/* just read the register -- rely on the core mode being right */
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static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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{
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uint32_t value;
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int retval;
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switch (regnum) {
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case 0 ... 14:
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/* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
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retval = dpm->instr_read_data_dcc(dpm,
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ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
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&value);
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break;
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case 15: /* PC */
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/* "MOV r0, pc"; then return via DCC */
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retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
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/* NOTE: this seems like a slightly awkward place to update
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* this value ... but if the PC gets written (the only way
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* to change what we compute), the arch spec says subsequent
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* reads return values which are "unpredictable". So this
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* is always right except in those broken-by-intent cases.
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*/
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switch (dpm->arm->core_state) {
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case ARMV4_5_STATE_ARM:
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value -= 8;
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break;
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case ARMV4_5_STATE_THUMB:
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case ARM_STATE_THUMB_EE:
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value -= 4;
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break;
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case ARMV4_5_STATE_JAZELLE:
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/* core-specific ... ? */
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LOG_WARNING("Jazelle PC adjustment unknown");
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break;
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}
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break;
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default:
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/* 16: "MRS r0, CPSR"; then return via DCC
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* 17: "MRS r0, SPSR"; then return via DCC
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*/
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retval = dpm->instr_read_data_r0(dpm,
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ARMV4_5_MRS(0, regnum & 1),
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&value);
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break;
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}
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if (retval == ERROR_OK) {
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buf_set_u32(r->value, 0, 32, value);
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r->valid = true;
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r->dirty = false;
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LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
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}
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return retval;
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}
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/* just write the register -- rely on the core mode being right */
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static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
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{
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int retval;
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uint32_t value = buf_get_u32(r->value, 0, 32);
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switch (regnum) {
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case 0 ... 14:
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/* load register from DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
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retval = dpm->instr_write_data_dcc(dpm,
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ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
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value);
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break;
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case 15: /* PC */
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/* read r0 from DCC; then "MOV pc, r0" */
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retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
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break;
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default:
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/* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
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* 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
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value);
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/* REVISIT on Cortex-A8, we need a Prefetch Flush operation
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* after writing CPSR ...
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cortex_a8_exec_opcode(target,
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ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
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*/
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break;
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}
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if (retval == ERROR_OK) {
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r->dirty = false;
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LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
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}
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return retval;
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}
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/**
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* Read basic registers of the the current context: R0 to R15, and CPSR;
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* sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
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* In normal operation this is called on entry to halting debug state,
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* possibly after some other operations supporting restore of debug state
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* or making sure the CPU is fully idle (drain write buffer, etc).
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*/
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int arm_dpm_read_current_registers(struct arm_dpm *dpm)
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{
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struct arm *arm = dpm->arm;
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uint32_t cpsr;
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int retval;
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struct reg *r;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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return retval;
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/* read R0 first (it's used for scratch), then CPSR */
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r = arm->core_cache->reg_list + 0;
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if (!r->valid) {
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retval = dpm_read_reg(dpm, r, 0);
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if (retval != ERROR_OK)
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goto fail;
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}
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r->dirty = true;
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retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
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if (retval != ERROR_OK)
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goto fail;
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/* update core mode and state, plus shadow mapping for R8..R14 */
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arm_set_cpsr(arm, cpsr);
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/* REVISIT we can probably avoid reading R1..R14, saving time... */
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for (unsigned i = 1; i < 16; i++) {
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r = arm_reg_current(arm, i);
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if (r->valid)
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continue;
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retval = dpm_read_reg(dpm, r, i);
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if (retval != ERROR_OK)
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goto fail;
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}
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/* NOTE: SPSR ignored (if it's even relevant). */
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fail:
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/* (void) */ dpm->finish(dpm);
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return retval;
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}
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/**
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* Writes all modified core registers for all processor modes. In normal
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* operation this is called on exit from halting debug state.
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*/
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int arm_dpm_write_dirty_registers(struct arm_dpm *dpm)
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{
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struct arm *arm = dpm->arm;
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struct reg_cache *cache = arm->core_cache;
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int retval;
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bool did_write;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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/* Scan the registers until we find one that's both dirty and
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* eligible for flushing. Flush that and everything else that
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* shares the same core mode setting. Typically this won't
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* actually find anything to do...
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*/
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do {
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enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
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did_write = false;
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/* check everything except our scratch register R0 */
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for (unsigned i = 1; i < cache->num_regs; i++) {
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struct arm_reg *r;
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unsigned regnum;
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/* also skip PC, CPSR, and non-dirty */
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if (i == 15)
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continue;
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if (arm->cpsr == cache->reg_list + i)
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continue;
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if (!cache->reg_list[i].dirty)
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continue;
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r = cache->reg_list[i].arch_info;
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regnum = r->num;
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/* may need to pick and set a mode */
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if (!did_write) {
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enum armv4_5_mode tmode;
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did_write = true;
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mode = tmode = r->mode;
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/* cope with special cases */
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switch (regnum) {
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case 8 ... 12:
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/* r8..r12 "anything but FIQ" case;
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* we "know" core mode is accurate
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* since we haven't changed it yet
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*/
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if (arm->core_mode == ARMV4_5_MODE_FIQ
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&& ARMV4_5_MODE_ANY
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!= mode)
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tmode = ARMV4_5_MODE_USR;
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break;
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case 16:
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/* SPSR */
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regnum++;
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break;
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}
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/* REVISIT error checks */
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if (tmode != ARMV4_5_MODE_ANY)
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retval = dpm_modeswitch(dpm, tmode);
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}
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if (r->mode != mode)
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continue;
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retval = dpm_write_reg(dpm,
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&cache->reg_list[i],
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regnum);
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}
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} while (did_write);
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/* Restore original CPSR ... assuming either that we changed it,
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* or it's dirty. Must write PC to ensure the return address is
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* defined, and must not write it before CPSR.
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*/
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retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
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arm->cpsr->dirty = false;
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retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
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cache->reg_list[15].dirty = false;
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/* flush R0 -- it's *very* dirty by now */
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retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
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cache->reg_list[0].dirty = false;
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/* (void) */ dpm->finish(dpm);
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done:
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return retval;
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}
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/* Returns ARMV4_5_MODE_ANY or temporary mode to use while reading the
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* specified register ... works around flakiness from ARM core calls.
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* Caller already filtered out SPSR access; mode is never MODE_SYS
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* or MODE_ANY.
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*/
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static enum armv4_5_mode dpm_mapmode(struct arm *arm,
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unsigned num, enum armv4_5_mode mode)
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{
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enum armv4_5_mode amode = arm->core_mode;
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/* don't switch if the mode is already correct */
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if (amode == ARMV4_5_MODE_SYS)
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amode = ARMV4_5_MODE_USR;
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if (mode == amode)
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return ARMV4_5_MODE_ANY;
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switch (num) {
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/* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
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case 0 ... 7:
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case 15:
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case 16:
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break;
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/* r8..r12 aren't shadowed for anything except FIQ */
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case 8 ... 12:
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if (mode == ARMV4_5_MODE_FIQ)
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return mode;
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break;
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/* r13/sp, and r14/lr are always shadowed */
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case 13:
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case 14:
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return mode;
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default:
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LOG_WARNING("invalid register #%u", num);
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break;
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}
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return ARMV4_5_MODE_ANY;
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}
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static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
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int regnum, enum armv4_5_mode mode)
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{
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struct arm_dpm *dpm = target_to_arm(target)->dpm;
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int retval;
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if (regnum < 0 || regnum > 16)
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return ERROR_INVALID_ARGUMENTS;
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if (regnum == 16) {
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if (mode != ARMV4_5_MODE_ANY)
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regnum = 17;
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} else
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mode = dpm_mapmode(dpm->arm, regnum, mode);
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/* REVISIT what happens if we try to read SPSR in a core mode
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* which has no such register?
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*/
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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return retval;
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if (mode != ARMV4_5_MODE_ANY) {
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retval = dpm_modeswitch(dpm, mode);
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if (retval != ERROR_OK)
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goto fail;
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}
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retval = dpm_read_reg(dpm, r, regnum);
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/* always clean up, regardless of error */
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if (mode != ARMV4_5_MODE_ANY)
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/* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
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fail:
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/* (void) */ dpm->finish(dpm);
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return retval;
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}
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static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
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int regnum, enum armv4_5_mode mode, uint32_t value)
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{
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struct arm_dpm *dpm = target_to_arm(target)->dpm;
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int retval;
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if (regnum < 0 || regnum > 16)
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return ERROR_INVALID_ARGUMENTS;
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if (regnum == 16) {
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if (mode != ARMV4_5_MODE_ANY)
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regnum = 17;
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} else
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mode = dpm_mapmode(dpm->arm, regnum, mode);
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/* REVISIT what happens if we try to write SPSR in a core mode
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* which has no such register?
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*/
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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return retval;
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if (mode != ARMV4_5_MODE_ANY) {
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retval = dpm_modeswitch(dpm, mode);
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if (retval != ERROR_OK)
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goto fail;
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}
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retval = dpm_write_reg(dpm, r, regnum);
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/* always clean up, regardless of error */
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if (mode != ARMV4_5_MODE_ANY)
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/* (void) */ dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
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fail:
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/* (void) */ dpm->finish(dpm);
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return retval;
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}
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static int arm_dpm_full_context(struct target *target)
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{
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struct arm *arm = target_to_arm(target);
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struct arm_dpm *dpm = arm->dpm;
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struct reg_cache *cache = arm->core_cache;
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int retval;
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bool did_read;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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do {
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enum armv4_5_mode mode = ARMV4_5_MODE_ANY;
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did_read = false;
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/* We "know" arm_dpm_read_current_registers() was called so
|
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* the unmapped registers (R0..R7, PC, AND CPSR) and some
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* view of R8..R14 are current. We also "know" oddities of
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* register mapping: special cases for R8..R12 and SPSR.
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*
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||||
* Pick some mode with unread registers and read them all.
|
||||
* Repeat until done.
|
||||
*/
|
||||
for (unsigned i = 0; i < cache->num_regs; i++) {
|
||||
struct arm_reg *r;
|
||||
|
||||
if (cache->reg_list[i].valid)
|
||||
continue;
|
||||
r = cache->reg_list[i].arch_info;
|
||||
|
||||
/* may need to pick a mode and set CPSR */
|
||||
if (!did_read) {
|
||||
did_read = true;
|
||||
mode = r->mode;
|
||||
|
||||
/* For R8..R12 when we've entered debug
|
||||
* state in FIQ mode... patch mode.
|
||||
*/
|
||||
if (mode == ARMV4_5_MODE_ANY)
|
||||
mode = ARMV4_5_MODE_USR;
|
||||
|
||||
/* REVISIT error checks */
|
||||
retval = dpm_modeswitch(dpm, mode);
|
||||
}
|
||||
if (r->mode != mode)
|
||||
continue;
|
||||
|
||||
/* CPSR was read, so "R16" must mean SPSR */
|
||||
retval = dpm_read_reg(dpm,
|
||||
&cache->reg_list[i],
|
||||
(r->num == 16) ? 17 : r->num);
|
||||
|
||||
}
|
||||
|
||||
} while (did_read);
|
||||
|
||||
retval = dpm_modeswitch(dpm, ARMV4_5_MODE_ANY);
|
||||
/* (void) */ dpm->finish(dpm);
|
||||
done:
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* Hooks up this DPM to its associated target; call only once.
|
||||
* Initially this only covers the register cache.
|
||||
*/
|
||||
int arm_dpm_setup(struct arm_dpm *dpm)
|
||||
{
|
||||
struct arm *arm = dpm->arm;
|
||||
struct target *target = arm->target;
|
||||
struct reg_cache *cache;
|
||||
|
||||
arm->dpm = dpm;
|
||||
|
||||
arm->full_context = arm_dpm_full_context;
|
||||
arm->read_core_reg = arm_dpm_read_core_reg;
|
||||
arm->write_core_reg = arm_dpm_write_core_reg;
|
||||
|
||||
cache = armv4_5_build_reg_cache(target, arm);
|
||||
if (!cache)
|
||||
return ERROR_FAIL;
|
||||
|
||||
*register_get_last_cache_p(&target->reg_cache) = cache;
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Reinitializes DPM state at the beginning of a new debug session
|
||||
* or after a reset which may have affected the debug module.
|
||||
*/
|
||||
int arm_dpm_initialize(struct arm_dpm *dpm)
|
||||
{
|
||||
/* FIXME -- nothing yet */
|
||||
return ERROR_OK;
|
||||
}
|
||||
87
src/target/arm_dpm.h
Normal file
87
src/target/arm_dpm.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (C) 2009 by David Brownell
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the
|
||||
* Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ARM_DPM_H
|
||||
#define __ARM_DPM_H
|
||||
|
||||
/**
|
||||
* @file
|
||||
* This is the interface to the Debug Programmers Model for ARMv6 and
|
||||
* ARMv7 processors. ARMv6 processors (such as ARM11xx implementations)
|
||||
* introduced a model which became part of the ARMv7-AR architecture
|
||||
* which is most familiar through the Cortex-A series parts. While
|
||||
* specific details differ (like how to write the instruction register),
|
||||
* the high level models easily support shared code because those
|
||||
* registers are compatible.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This wraps an implementation of DPM primitives. Each interface
|
||||
* provider supplies a structure like this, which is the glue between
|
||||
* upper level code and the lower level hardware access.
|
||||
*
|
||||
* It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
|
||||
* support for CPU register access.
|
||||
*/
|
||||
struct arm_dpm {
|
||||
struct arm *arm;
|
||||
|
||||
/** Cache of DIDR */
|
||||
uint32_t didr;
|
||||
|
||||
/** Invoke before a series of instruction operations */
|
||||
int (*prepare)(struct arm_dpm *);
|
||||
|
||||
/** Invoke after a series of instruction operations */
|
||||
int (*finish)(struct arm_dpm *);
|
||||
|
||||
/* WRITE TO CPU */
|
||||
|
||||
/** Runs one instruction, writing data to DCC before execution. */
|
||||
int (*instr_write_data_dcc)(struct arm_dpm *,
|
||||
uint32_t opcode, uint32_t data);
|
||||
|
||||
/** Runs one instruction, writing data to R0 before execution. */
|
||||
int (*instr_write_data_r0)(struct arm_dpm *,
|
||||
uint32_t opcode, uint32_t data);
|
||||
|
||||
/* READ FROM CPU */
|
||||
|
||||
/** Runs one instruction, reading data from dcc after execution. */
|
||||
int (*instr_read_data_dcc)(struct arm_dpm *,
|
||||
uint32_t opcode, uint32_t *data);
|
||||
|
||||
/** Runs one instruction, reading data from r0 after execution. */
|
||||
int (*instr_read_data_r0)(struct arm_dpm *,
|
||||
uint32_t opcode, uint32_t *data);
|
||||
|
||||
// FIXME -- add breakpoint support
|
||||
|
||||
// FIXME -- add watchpoint support (including context-sensitive ones)
|
||||
|
||||
// FIXME -- read/write DCSR methods and symbols
|
||||
};
|
||||
|
||||
int arm_dpm_setup(struct arm_dpm *dpm);
|
||||
int arm_dpm_reinitialize(struct arm_dpm *dpm);
|
||||
|
||||
int arm_dpm_read_current_registers(struct arm_dpm *);
|
||||
int arm_dpm_write_dirty_registers(struct arm_dpm *);
|
||||
|
||||
#endif /* __ARM_DPM_H */
|
||||
|
|
@ -1233,6 +1233,7 @@ static int arm_full_context(struct target *target)
|
|||
int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
|
||||
{
|
||||
target->arch_info = armv4_5;
|
||||
armv4_5->target = target;
|
||||
|
||||
armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
|
||||
arm_set_cpsr(armv4_5, ARMV4_5_MODE_USR);
|
||||
|
|
|
|||
|
|
@ -101,6 +101,12 @@ struct arm
|
|||
/** Flag reporting unavailability of the BKPT instruction. */
|
||||
bool is_armv4;
|
||||
|
||||
/** Backpointer to the target. */
|
||||
struct target *target;
|
||||
|
||||
/** Handle for the debug module, if one is present. */
|
||||
struct arm_dpm *dpm;
|
||||
|
||||
/** Handle for the Embedded Trace Module, if one is present. */
|
||||
struct etm_context *etm;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user