David Brownell <david-b@pacbell.net>:
Start converting the architecture-specific commands to @deffn format,
reviewing against the code.
* armv4_5 disassemble ... now documented; although Jazelle code
is not handled
* It's "armv4_5 core_state" not "core_mode"; although Jazelle state
is not handled
* arm7/9 "debug" commands ... now with other arm7_9 commands, no
longer in a separate section
* arm926ejs cp15 ... previous description was broken, it matched
the code for arm920t instead
* Have separate subsections for ARMv4/ARMv5, ARMv6, and ARMv7; the
latter are new
* Move core-specific descriptions into sub-subsections under those
architectures; XScale and ARM11 descriptions are new
The new XScale and ARM11 command descriptions surely need elaboration
and review. ARM CP15 operation descriptions in general seem to be
confused and incomplete.
git-svn-id: svn://svn.berlios.de/openocd/trunk@1939 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
zwelch
parent
6149c509ca
commit
ea62c7964a
522
doc/openocd.texi
522
doc/openocd.texi
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@ -2482,8 +2482,9 @@ Write the image @file{filename} to the current target's flash bank(s).
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A relocation @var{offset} may be specified, in which case it is added
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to the base address for each section in the image.
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The file [@var{type}] can be specified
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explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
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(ELF file) or @option{s19} (Motorola s19).
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explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
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@option{elf} (ELF file), @option{s19} (Motorola s19).
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@option{mem}, or @option{builder}.
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The relevant flash sectors will be erased prior to programming
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if the @option{erase} parameter is given.
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The flash bank to use is inferred from the @var{address} of
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@ -3463,188 +3464,403 @@ Profiling samples the CPU's program counter as quickly as possible, which is use
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@end itemize
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@section Target Specific Commands
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@cindex Target Specific Commands
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@section Architecture Specific Commands
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@section Architecture and Core Specific Commands
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@cindex Architecture Specific Commands
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@cindex Core Specific Commands
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@subsection ARMV4/5 specific commands
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@cindex ARMV4/5 specific commands
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Most CPUs have specialized JTAG operations to support debugging.
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OpenOCD packages most such operations in its standard command framework.
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Some of those operations don't fit well in that framework, so they are
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exposed here using architecture or implementation specific commands.
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These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
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or Intel XScale (XScale isn't supported yet).
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@itemize @bullet
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@item @b{armv4_5 reg}
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@cindex armv4_5 reg
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@*Display a list of all banked core registers, fetching the current value from every
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@subsection ARMv4 and ARMv5 Architecture
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@cindex ARMv4 specific commands
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@cindex ARMv5 specific commands
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These commands are specific to ARM architecture v4 and v5,
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including all ARM7 or ARM9 systems and Intel XScale.
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They are available in addition to other core-specific
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commands that may be available.
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@deffn Command {armv4_5 core_state} [arm|thumb]
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Displays the core_state, optionally changing it to process
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either @option{arm} or @option{thumb} instructions.
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The target may later be resumed in the currently set core_state.
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(Processors may also support the Jazelle state, but
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that is not currently supported in OpenOCD.)
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@end deffn
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@deffn Command {armv4_5 disassemble} address count [thumb]
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@cindex disassemble
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Disassembles @var{count} instructions starting at @var{address}.
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If @option{thumb} is specified, Thumb (16-bit) instructions are used;
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else ARM (32-bit) instructions are used.
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(Processors may also support the Jazelle state, but
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those instructions are not currently understood by OpenOCD.)
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@end deffn
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@deffn Command {armv4_5 reg}
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Display a list of all banked core registers, fetching the current value from every
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core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
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register value.
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@item @b{armv4_5 core_mode} [@var{arm}|@var{thumb}]
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@cindex armv4_5 core_mode
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@*Displays the core_mode, optionally changing it to either ARM or Thumb mode.
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The target is resumed in the currently set @option{core_mode}.
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@end itemize
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@end deffn
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@subsection ARM7/9 specific commands
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@cindex ARM7/9 specific commands
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@subsubsection ARM7 and ARM9 specific commands
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@cindex ARM7 specific commands
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@cindex ARM9 specific commands
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These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
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ARM920T or ARM926EJ-S.
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@itemize @bullet
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@item @b{arm7_9 dbgrq} <@var{enable}|@var{disable}>
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@cindex arm7_9 dbgrq
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@*Enable use of the DBGRQ bit to force entry into debug mode. This should be
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These commands are specific to ARM7 and ARM9 cores, like ARM7TDMI, ARM720T,
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ARM9TDMI, ARM920T or ARM926EJ-S.
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They are available in addition to the ARMv4/5 commands,
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and any other core-specific commands that may be available.
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@deffn Command {arm7_9 dbgrq} (enable|disable)
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Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
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instead of breakpoints. This should be
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safe for all but ARM7TDMI--S cores (like Philips LPC).
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@item @b{arm7_9 fast_memory_access} <@var{enable}|@var{disable}>
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@cindex arm7_9 fast_memory_access
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@end deffn
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@deffn Command {arm7_9 dcc_downloads} (enable|disable)
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@cindex DCC
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Control the use of the debug communications channel (DCC) to write larger (>128 byte)
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amounts of memory. DCC downloads offer a huge speed increase, but might be
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unsafe, especially with targets running at very low speeds. This command was introduced
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with OpenOCD rev. 60, and requires a few bytes of working area.
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@end deffn
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@anchor{arm7_9 fast_memory_access}
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@*Allow OpenOCD to read and write memory without checking completion of
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@deffn Command {arm7_9 fast_memory_access} (enable|disable)
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Enable or disable memory writes and reads that don't check completion of
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the operation. This provides a huge speed increase, especially with USB JTAG
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cables (FT2232), but might be unsafe if used with targets running at very low
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speeds, like the 32kHz startup clock of an AT91RM9200.
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@item @b{arm7_9 dcc_downloads} <@var{enable}|@var{disable}>
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@cindex arm7_9 dcc_downloads
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@*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
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amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
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unsafe, especially with targets running at very low speeds. This command was introduced
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with OpenOCD rev. 60, and requires a few bytes of working area.
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@end itemize
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@end deffn
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@subsection ARM720T specific commands
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@deffn {Debug Command} {arm7_9 write_core_reg} num mode word
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@emph{This is intended for use while debugging OpenOCD; you probably
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shouldn't use it.}
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Writes a 32-bit @var{word} to register @var{num} (from 0 to 16)
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as used in the specified @var{mode}
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(where e.g. mode 16 is "user" and mode 19 is "supervisor";
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the M4..M0 bits of the PSR).
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Registers 0..15 are the normal CPU registers such as r0(0), r1(1) ... pc(15).
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Register 16 is the mode-specific SPSR,
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unless the specified mode is 0xffffffff (32-bit all-ones)
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in which case register 16 is the CPSR.
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The write goes directly to the CPU, bypassing the register cache.
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@end deffn
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@deffn {Debug Command} {arm7_9 write_xpsr} word (0|1)
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@emph{This is intended for use while debugging OpenOCD; you probably
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shouldn't use it.}
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If the second parameter is zero, writes @var{word} to the
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Current Program Status register (CPSR).
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Else writes @var{word} to the current mode's Saved PSR (SPSR).
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In both cases, this bypasses the register cache.
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@end deffn
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@deffn {Debug Command} {arm7_9 write_xpsr_im8} byte rotate (0|1)
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@emph{This is intended for use while debugging OpenOCD; you probably
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shouldn't use it.}
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Writes eight bits to the CPSR or SPSR,
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first rotating them by @math{2*rotate} bits,
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and bypassing the register cache.
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This has lower JTAG overhead than writing the entire CPSR or SPSR
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with @command{arm7_9 write_xpsr}.
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@end deffn
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@subsubsection ARM720T specific commands
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@cindex ARM720T specific commands
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@itemize @bullet
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@item @b{arm720t cp15} <@var{num}> [@var{value}]
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@cindex arm720t cp15
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@*display/modify cp15 register <@option{num}> [@option{value}].
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@item @b{arm720t md<bhw>_phys} <@var{addr}> [@var{count}]
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@cindex arm720t md<bhw>_phys
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@*Display memory at physical address addr.
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@item @b{arm720t mw<bhw>_phys} <@var{addr}> <@var{value}>
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@cindex arm720t mw<bhw>_phys
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@*Write memory at physical address addr.
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@item @b{arm720t virt2phys} <@var{va}>
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@cindex arm720t virt2phys
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@*Translate a virtual address to a physical address.
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@end itemize
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These commands are available to ARM720T based CPUs,
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which are implementations of the ARMv4T architecture
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based on the ARM7TDMI-S integer core.
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They are available in addition to the ARMv4/5 and ARM7/ARM9 commands.
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@subsection ARM9TDMI specific commands
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@deffn Command {arm720t cp15} regnum [value]
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Display cp15 register @var{regnum};
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else if a @var{value} is provided, that value is written to that register.
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@end deffn
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@deffn Command {arm720t mdw_phys} addr [count]
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@deffnx Command {arm720t mdh_phys} addr [count]
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@deffnx Command {arm720t mdb_phys} addr [count]
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Display contents of physical address @var{addr}, as
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32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
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or 8-bit bytes (@command{mdb_phys}).
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If @var{count} is specified, displays that many units.
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@end deffn
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@deffn Command {arm720t mww_phys} addr word
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@deffnx Command {arm720t mwh_phys} addr halfword
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@deffnx Command {arm720t mwb_phys} addr byte
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Writes the specified @var{word} (32 bits),
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@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
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at the specified physical address @var{addr}.
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@end deffn
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@deffn Command {arm720t virt2phys} va
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Translate a virtual address @var{va} to a physical address
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and display the result.
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@end deffn
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@subsubsection ARM9TDMI specific commands
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@cindex ARM9TDMI specific commands
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@itemize @bullet
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@item @b{arm9tdmi vector_catch} <@var{all}|@var{none}>
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@cindex arm9tdmi vector_catch
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@*Catch arm9 interrupt vectors, can be @option{all} @option{none} or any of the following:
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Many ARM9-family CPUs are built around ARM9TDMI integer cores,
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or processors resembling ARM9TDMI, and can use these commands.
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Such cores include the ARM920T, ARM926EJ-S, and ARM966.
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@deffn Command {arm9tdmi vector_catch} (all|none|list)
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Catch arm9 interrupt vectors, can be @option{all}, @option{none},
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or a list with one or more of the following:
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@option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
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@option{irq} @option{fiq}.
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@end deffn
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Can also be used on other ARM9 based cores such as ARM966, ARM920T and ARM926EJ-S.
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@end itemize
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@subsection ARM966E specific commands
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@cindex ARM966E specific commands
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@itemize @bullet
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@item @b{arm966e cp15} <@var{num}> [@var{value}]
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@cindex arm966e cp15
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@*display/modify cp15 register <@option{num}> [@option{value}].
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@end itemize
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@subsection ARM920T specific commands
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@subsubsection ARM920T specific commands
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@cindex ARM920T specific commands
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@itemize @bullet
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@item @b{arm920t cp15} <@var{num}> [@var{value}]
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@cindex arm920t cp15
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@*display/modify cp15 register <@option{num}> [@option{value}].
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@item @b{arm920t cp15i} <@var{num}> [@var{value}] [@var{address}]
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@cindex arm920t cp15i
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@*display/modify cp15 (interpreted access) <@option{opcode}> [@option{value}] [@option{address}]
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@item @b{arm920t cache_info}
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@cindex arm920t cache_info
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@*Print information about the caches found. This allows to see whether your target
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is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
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@item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
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@cindex arm920t md<bhw>_phys
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@*Display memory at physical address addr.
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@item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
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@cindex arm920t mw<bhw>_phys
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@*Write memory at physical address addr.
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@item @b{arm920t read_cache} <@var{filename}>
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@cindex arm920t read_cache
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@*Dump the content of ICache and DCache to a file.
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@item @b{arm920t read_mmu} <@var{filename}>
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@cindex arm920t read_mmu
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@*Dump the content of the ITLB and DTLB to a file.
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@item @b{arm920t virt2phys} <@var{va}>
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@cindex arm920t virt2phys
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@*Translate a virtual address to a physical address.
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@end itemize
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These commands are available to ARM920T based CPUs,
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which are implementations of the ARMv4T architecture
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built using the ARM9TDMI integer core.
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They are available in addition to the ARMv4/5, ARM7/ARM9,
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and ARM9TDMI commands.
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@subsection ARM926EJ-S specific commands
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@deffn Command {arm920t cache_info}
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Print information about the caches found. This allows to see whether your target
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is an ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
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@end deffn
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@deffn Command {arm920t cp15} regnum [value]
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Display cp15 register @var{regnum};
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else if a @var{value} is provided, that value is written to that register.
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@end deffn
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@deffn Command {arm920t cp15i} opcode [value [address]]
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Interpreted access using cp15 @var{opcode}.
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If no @var{value} is provided, the result is displayed.
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Else if that value is written using the specified @var{address},
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or using zero if no other address is not provided.
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@end deffn
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@deffn Command {arm920t mdw_phys} addr [count]
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@deffnx Command {arm920t mdh_phys} addr [count]
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@deffnx Command {arm920t mdb_phys} addr [count]
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Display contents of physical address @var{addr}, as
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32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
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or 8-bit bytes (@command{mdb_phys}).
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If @var{count} is specified, displays that many units.
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@end deffn
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@deffn Command {arm920t mww_phys} addr word
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@deffnx Command {arm920t mwh_phys} addr halfword
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@deffnx Command {arm920t mwb_phys} addr byte
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Writes the specified @var{word} (32 bits),
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@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
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at the specified physical address @var{addr}.
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@end deffn
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@deffn Command {arm920t read_cache} filename
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Dump the content of ICache and DCache to a file named @file{filename}.
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@end deffn
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@deffn Command {arm920t read_mmu} filename
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Dump the content of the ITLB and DTLB to a file named @file{filename}.
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@end deffn
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@deffn Command {arm920t virt2phys} @var{va}
|
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Translate a virtual address @var{va} to a physical address
|
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and display the result.
|
||||
@end deffn
|
||||
|
||||
@subsubsection ARM926EJ-S specific commands
|
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@cindex ARM926EJ-S specific commands
|
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|
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@itemize @bullet
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@item @b{arm926ejs cp15} <@var{num}> [@var{value}]
|
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@cindex arm926ejs cp15
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@*display/modify cp15 register <@option{num}> [@option{value}].
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@item @b{arm926ejs cache_info}
|
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@cindex arm926ejs cache_info
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@*Print information about the caches found.
|
||||
@item @b{arm926ejs md<bhw>_phys} <@var{addr}> [@var{count}]
|
||||
@cindex arm926ejs md<bhw>_phys
|
||||
@*Display memory at physical address addr.
|
||||
@item @b{arm926ejs mw<bhw>_phys} <@var{addr}> <@var{value}>
|
||||
@cindex arm926ejs mw<bhw>_phys
|
||||
@*Write memory at physical address addr.
|
||||
@item @b{arm926ejs virt2phys} <@var{va}>
|
||||
@cindex arm926ejs virt2phys
|
||||
@*Translate a virtual address to a physical address.
|
||||
@end itemize
|
||||
These commands are available to ARM926EJ-S based CPUs,
|
||||
which are implementations of the ARMv5TEJ architecture
|
||||
based on the ARM9EJ-S integer core.
|
||||
They are available in addition to the ARMv4/5, ARM7/ARM9,
|
||||
and ARM9TDMI commands.
|
||||
|
||||
@subsection CORTEX_M3 specific commands
|
||||
@cindex CORTEX_M3 specific commands
|
||||
@deffn Command {arm926ejs cache_info}
|
||||
Print information about the caches found.
|
||||
@end deffn
|
||||
|
||||
@itemize @bullet
|
||||
@item @b{cortex_m3 maskisr} <@var{on}|@var{off}>
|
||||
@cindex cortex_m3 maskisr
|
||||
@*Enable masking (disabling) interrupts during target step/resume.
|
||||
@end itemize
|
||||
@deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
|
||||
Accesses cp15 register @var{regnum} using
|
||||
@var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
|
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If a @var{value} is provided, that value is written to that register.
|
||||
Else that register is read and displayed.
|
||||
@end deffn
|
||||
|
||||
@page
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@section Debug commands
|
||||
@cindex Debug commands
|
||||
The following commands give direct access to the core, and are most likely
|
||||
only useful while debugging OpenOCD.
|
||||
@itemize @bullet
|
||||
@item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
|
||||
@cindex arm7_9 write_xpsr
|
||||
@*Immediately write either the current program status register (CPSR) or the saved
|
||||
program status register (SPSR), without changing the register cache (as displayed
|
||||
by the @option{reg} and @option{armv4_5 reg} commands).
|
||||
@item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
|
||||
<@var{0=cpsr},@var{1=spsr}>
|
||||
@cindex arm7_9 write_xpsr_im8
|
||||
@*Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
|
||||
operation (similar to @option{write_xpsr}).
|
||||
@item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
|
||||
@cindex arm7_9 write_core_reg
|
||||
@*Write a core register, without changing the register cache (as displayed by the
|
||||
@option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
|
||||
encoding of the [M4:M0] bits of the PSR.
|
||||
@end itemize
|
||||
@deffn Command {arm926ejs mdw_phys} addr [count]
|
||||
@deffnx Command {arm926ejs mdh_phys} addr [count]
|
||||
@deffnx Command {arm926ejs mdb_phys} addr [count]
|
||||
Display contents of physical address @var{addr}, as
|
||||
32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
|
||||
or 8-bit bytes (@command{mdb_phys}).
|
||||
If @var{count} is specified, displays that many units.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {arm926ejs mww_phys} addr word
|
||||
@deffnx Command {arm926ejs mwh_phys} addr halfword
|
||||
@deffnx Command {arm926ejs mwb_phys} addr byte
|
||||
Writes the specified @var{word} (32 bits),
|
||||
@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
|
||||
at the specified physical address @var{addr}.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {arm926ejs virt2phys} @var{va}
|
||||
Translate a virtual address @var{va} to a physical address
|
||||
and display the result.
|
||||
@end deffn
|
||||
|
||||
@subsubsection ARM966E specific commands
|
||||
@cindex ARM966E specific commands
|
||||
|
||||
These commands are available to ARM966 based CPUs,
|
||||
which are implementations of the ARMv5TE architecture.
|
||||
They are available in addition to the ARMv4/5, ARM7/ARM9,
|
||||
and ARM9TDMI commands.
|
||||
|
||||
@deffn Command {arm966e cp15} regnum [value]
|
||||
Display cp15 register @var{regnum};
|
||||
else if a @var{value} is provided, that value is written to that register.
|
||||
@end deffn
|
||||
|
||||
@subsubsection XScale specific commands
|
||||
@cindex XScale specific commands
|
||||
|
||||
These commands are available to XScale based CPUs,
|
||||
which are implementations of the ARMv5TE architecture.
|
||||
|
||||
@deffn Command {xscale analyze_trace}
|
||||
Displays the contents of the trace buffer.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale cache_clean_address} address
|
||||
Changes the address used when cleaning the data cache.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale cache_info}
|
||||
Displays information about the CPU caches.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale cp15} regnum [value]
|
||||
Display cp15 register @var{regnum};
|
||||
else if a @var{value} is provided, that value is written to that register.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale debug_handler} target address
|
||||
Changes the address used for the specified target's debug handler.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale dcache} (enable|disable)
|
||||
Enables or disable the CPU's data cache.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale dump_trace} filename
|
||||
Dumps the raw contents of the trace buffer to @file{filename}.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale icache} (enable|disable)
|
||||
Enables or disable the CPU's instruction cache.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale mmu} (enable|disable)
|
||||
Enables or disable the CPU's memory management unit.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale trace_buffer} (enable|disable) [fill [n] | wrap]
|
||||
Enables or disables the trace buffer,
|
||||
and controls how it is emptied.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale trace_image} filename [offset [type]]
|
||||
Opens a trace image from @file{filename}, optionally rebasing
|
||||
its segment addresses by @var{offset}.
|
||||
The image @var{type} may be one of
|
||||
@option{bin} (binary), @option{ihex} (Intel hex),
|
||||
@option{elf} (ELF file), @option{s19} (Motorola s19),
|
||||
@option{mem}, or @option{builder}.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {xscale vector_catch} mask
|
||||
Provide a bitmask showing the vectors to catch.
|
||||
@end deffn
|
||||
|
||||
@subsection ARMv6 Architecture
|
||||
|
||||
@subsubsection ARM11 specific commands
|
||||
@cindex ARM11 specific commands
|
||||
|
||||
@deffn Command {arm11 mcr} p1 p2 p3 p4 p5
|
||||
Read coprocessor register
|
||||
@end deffn
|
||||
|
||||
@deffn Command {arm11 memwrite burst} [value]
|
||||
Displays the value of the memwrite burst-enable flag,
|
||||
which is enabled by default.
|
||||
If @var{value} is defined, first assigns that.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {arm11 memwrite error_fatal} [value]
|
||||
Displays the value of the memwrite error_fatal flag,
|
||||
which is enabled by default.
|
||||
If @var{value} is defined, first assigns that.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
|
||||
Write coprocessor register
|
||||
@end deffn
|
||||
|
||||
@deffn Command {arm11 no_increment} [value]
|
||||
Displays the value of the flag controlling whether
|
||||
some read or write operations increment the pointer
|
||||
(the default behavior) or not (acting like a FIFO).
|
||||
If @var{value} is defined, first assigns that.
|
||||
@end deffn
|
||||
|
||||
@deffn Command {arm11 step_irq_enable} [value]
|
||||
Displays the value of the flag controlling whether
|
||||
IRQs are enabled during single stepping;
|
||||
they is disabled by default.
|
||||
If @var{value} is defined, first assigns that.
|
||||
@end deffn
|
||||
|
||||
@subsection ARMv7 Architecture
|
||||
|
||||
@subsubsection Cortex-M3 specific commands
|
||||
@cindex Cortex-M3 specific commands
|
||||
|
||||
@deffn Command {cortex_m3 maskisr} (on|off)
|
||||
Control masking (disabling) interrupts during target step/resume.
|
||||
@end deffn
|
||||
|
||||
@section Target DCC Requests
|
||||
@cindex Linux-ARM DCC support
|
||||
@cindex libdcc
|
||||
@cindex DCC
|
||||
OpenOCD can handle certain target requests; currently debugmsgs
|
||||
@command{target_request debugmsgs}
|
||||
are only supported for arm7_9 and cortex_m3.
|
||||
|
||||
@section Target Requests
|
||||
@cindex Target Requests
|
||||
OpenOCD can handle certain target requests, currently debugmsg are only supported for arm7_9 and cortex_m3.
|
||||
See libdcc in the contrib dir for more details.
|
||||
@itemize @bullet
|
||||
@item @b{target_request debugmsgs} <@var{enable}|@var{disable}|@var{charmsg}>
|
||||
@cindex target_request debugmsgs
|
||||
@*Enable/disable target debugmsgs requests. debugmsgs enable messages to be sent to the debugger while the target is running. @var{charmsg} receives messages if Linux kernel ``Kernel low-level debugging via EmbeddedICE DCC channel'' option is enabled.
|
||||
@end itemize
|
||||
Linux-ARM kernels have a ``Kernel low-level debugging
|
||||
via EmbeddedICE DCC channel'' option (CONFIG_DEBUG_ICEDCC,
|
||||
depends on CONFIG_DEBUG_LL) which uses this mechanism to
|
||||
deliver messages before a serial console can be activated.
|
||||
|
||||
@deffn Command {target_request debugmsgs} [enable|disable|charmsg]
|
||||
Displays current handling of target DCC message requests.
|
||||
These messages may be sent to the debugger while the target is running.
|
||||
The optional @option{enable} and @option{charmsg} parameters are
|
||||
equivalent; both enable the messages, @option{disable} disables them.
|
||||
@end deffn
|
||||
|
||||
@node JTAG Commands
|
||||
@chapter JTAG Commands
|
||||
|
|
|
|||
Loading…
Reference in New Issue