imi415
/
openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/arc: refactor ARC register numbers defines 

For Zephyr rtos support it is necessary to define general register
numbers for architecture. There were some already in arc.h file.
Let's define ARC registers numbers as a set instead of separate defines.

Change-Id: I63742b8608f9556c2ec9bd2661a0fd9cf88e9b74
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/6105
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Evgeniy Didin 2021-03-15 16:30:13 +03:00 committed by Antonio Borneo
parent 6db49eb885
commit eca4f964b4
3 changed files with 51 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/target/arc.c
View File

@ -227,7 +227,7 @@ static int arc_get_register(struct reg *reg)
if (desc->is_core) {
/* Accessing to R61/R62 registers causes Jtag hang */
if (desc->arch_num == CORE_R61_NUM || desc->arch_num == CORE_R62_NUM) {
if (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62) {
LOG_ERROR("It is forbidden to read core registers 61 and 62.");
return ERROR_FAIL;
}
@ -267,8 +267,8 @@ static int arc_set_register(struct reg *reg, uint8_t *buf)
return ERROR_TARGET_NOT_HALTED;
/* Accessing to R61/R62 registers causes Jtag hang */
if (desc->is_core && (desc->arch_num == CORE_R61_NUM ||
desc->arch_num == CORE_R62_NUM)) {
if (desc->is_core && (desc->arch_num == ARC_R61 ||
desc->arch_num == ARC_R62)) {
LOG_ERROR("It is forbidden to write core registers 61 and 62.");
return ERROR_FAIL;
}

49
src/target/arc.h
View File

@ -45,9 +45,52 @@
#define AUX_STATUS32_REG_HALT_BIT BIT(0)
#define AUX_STATUS32_REG_IE_BIT BIT(31) /* STATUS32[31] = IE field */
/* Reserved core registers */
#define CORE_R61_NUM (61)
#define CORE_R62_NUM (62)
/* ARC register numbers */
enum {
ARC_R0,
ARC_R1,
ARC_R2,
ARC_R3,
ARC_R4,
ARC_R5,
ARC_R6,
ARC_R7,
ARC_R8,
ARC_R9,
ARC_R10,
ARC_R11,
ARC_R12,
ARC_R13,
ARC_R14,
ARC_R15,
ARC_R16,
ARC_R17,
ARC_R18,
ARC_R19,
ARC_R20,
ARC_R21,
ARC_R22,
ARC_R23,
ARC_R24,
ARC_R25,
ARC_GP = 26,
ARC_FP = 27,
ARC_SP = 28,
ARC_ILINK = 29,
ARC_R30,
ARC_BLINK = 31,
ARC_LP_COUNT = 60,
/* Reserved registers */
ARC_R61 = 61,
ARC_R62 = 62,
ARC_PCL = 63,
ARC_PC = 64,
ARC_LP_START = 65,
ARC_LP_END = 66,
ARC_STATUS32 = 67,
};
#define CORE_REG_MAX_NUMBER (63)

4
src/target/arc_cmd.c
View File

@ -382,7 +382,7 @@ static int jim_arc_get_core_reg(Jim_Interp *interp, int argc, Jim_Obj * const *a
/* Register number */
JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, &regnum));
if (regnum > CORE_REG_MAX_NUMBER || regnum == CORE_R61_NUM || regnum == CORE_R62_NUM) {
if (regnum > CORE_REG_MAX_NUMBER || regnum == ARC_R61 || regnum == ARC_R62) {
Jim_SetResultFormatted(goi.interp, "Core register number %i "
"is invalid. Must less then 64 and not 61 and 62.", regnum);
return JIM_ERR;
@ -425,7 +425,7 @@ static int jim_arc_set_core_reg(Jim_Interp *interp, int argc, Jim_Obj * const *a
/* Register number */
JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, &regnum));
if (regnum > CORE_REG_MAX_NUMBER || regnum == CORE_R61_NUM || regnum == CORE_R62_NUM) {
if (regnum > CORE_REG_MAX_NUMBER || regnum == ARC_R61 || regnum == ARC_R62) {
Jim_SetResultFormatted(goi.interp, "Core register number %i "
"is invalid. Must less then 64 and not 61 and 62.", regnum);
return JIM_ERR;