diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
new file mode 100644
index 000000000..1ea7a49e1
--- /dev/null
+++ b/tcl/target/lpc1850.cfg
@@ -0,0 +1,31 @@
+
+adapter_khz 500
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME lpc1850
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+#
+# M3 JTAG mode TAP
+#
+if { [info exists M3_JTAG_TAPID] } {
+   set _M3_JTAG_TAPID $M3_JTAG_TAPID
+} else {
+   set _M3_JTAG_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
+
+set _TARGETNAME $_CHIPNAME.m3
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq