imi415
/
openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

s3c24xx_nand_controller_t -> struct s3c24xx_nand_controller 

Remove misleading typedef and redundant suffix from struct s3c24xx_nand_controller.
This commit is contained in:
Zachary T Welch 2009-11-13 07:38:52 -08:00
parent eba5608b52
commit ed9c4ef3c4
6 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/flash/s3c2410_nand.c
View File

@ -32,7 +32,7 @@
NAND_DEVICE_COMMAND_HANDLER(s3c2410_nand_device_command)
{
s3c24xx_nand_controller_t *info;
struct s3c24xx_nand_controller *info;
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
@ -46,7 +46,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2410_nand_device_command)
static int s3c2410_init(struct nand_device_s *nand)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
@ -58,7 +58,7 @@ static int s3c2410_init(struct nand_device_s *nand)
static int s3c2410_write_data(struct nand_device_s *nand, uint16_t data)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
@ -72,7 +72,7 @@ static int s3c2410_write_data(struct nand_device_s *nand, uint16_t data)
static int s3c2410_read_data(struct nand_device_s *nand, void *data)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
@ -86,7 +86,7 @@ static int s3c2410_read_data(struct nand_device_s *nand, void *data)
static int s3c2410_nand_ready(struct nand_device_s *nand, int timeout)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
uint8_t status;

4
src/flash/s3c2412_nand.c
View File

@ -32,7 +32,7 @@
NAND_DEVICE_COMMAND_HANDLER(s3c2412_nand_device_command)
{
s3c24xx_nand_controller_t *info;
struct s3c24xx_nand_controller *info;
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
@ -46,7 +46,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2412_nand_device_command)
static int s3c2412_init(struct nand_device_s *nand)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,

10
src/flash/s3c2440_nand.c
View File

@ -33,7 +33,7 @@
NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
{
s3c24xx_nand_controller_t *info;
struct s3c24xx_nand_controller *info;
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
@ -47,7 +47,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2440_nand_device_command)
static int s3c2440_init(struct nand_device_s *nand)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,
@ -63,7 +63,7 @@ static int s3c2440_init(struct nand_device_s *nand)
int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
uint8_t status;
@ -89,7 +89,7 @@ int s3c2440_nand_ready(struct nand_device_s *nand, int timeout)
int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;
@ -125,7 +125,7 @@ int s3c2440_read_block_data(struct nand_device_s *nand, uint8_t *data, int data_
int s3c2440_write_block_data(struct nand_device_s *nand, uint8_t *data, int data_size)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
uint32_t nfdata = s3c24xx_info->data;
uint32_t tmp;

4
src/flash/s3c2443_nand.c
View File

@ -33,7 +33,7 @@
NAND_DEVICE_COMMAND_HANDLER(s3c2443_nand_device_command)
{
s3c24xx_nand_controller_t *info;
struct s3c24xx_nand_controller *info;
CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
/* fill in the address fields for the core device */
@ -47,7 +47,7 @@ NAND_DEVICE_COMMAND_HANDLER(s3c2443_nand_device_command)
static int s3c2443_init(struct nand_device_s *nand)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
target_write_u32(target, S3C2410_NFCONF,

14
src/flash/s3c24xx_nand.c
View File

@ -33,9 +33,9 @@
S3C24XX_DEVICE_COMMAND()
{
s3c24xx_nand_controller_t *s3c24xx_info;
struct s3c24xx_nand_controller *s3c24xx_info;
s3c24xx_info = malloc(sizeof(s3c24xx_nand_controller_t));
s3c24xx_info = malloc(sizeof(struct s3c24xx_nand_controller));
if (s3c24xx_info == NULL) {
LOG_ERROR("no memory for nand controller\n");
return -ENOMEM;
@ -59,7 +59,7 @@ int s3c24xx_register_commands(struct command_context_s *cmd_ctx)
int s3c24xx_reset(struct nand_device_s *nand)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
@ -74,7 +74,7 @@ int s3c24xx_reset(struct nand_device_s *nand)
int s3c24xx_command(struct nand_device_s *nand, uint8_t command)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
@ -89,7 +89,7 @@ int s3c24xx_command(struct nand_device_s *nand, uint8_t command)
int s3c24xx_address(struct nand_device_s *nand, uint8_t address)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
@ -103,7 +103,7 @@ int s3c24xx_address(struct nand_device_s *nand, uint8_t address)
int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {
@ -117,7 +117,7 @@ int s3c24xx_write_data(struct nand_device_s *nand, uint16_t data)
int s3c24xx_read_data(struct nand_device_s *nand, void *data)
{
s3c24xx_nand_controller_t *s3c24xx_info = nand->controller_priv;
struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
target_t *target = s3c24xx_info->target;
if (target->state != TARGET_HALTED) {

6
src/flash/s3c24xx_nand.h
View File

@ -30,7 +30,7 @@
#include "nand.h"
#include "s3c24xx_regs_nand.h"
typedef struct s3c24xx_nand_controller_s
struct s3c24xx_nand_controller
{
struct target_s *target;
@ -39,7 +39,7 @@ typedef struct s3c24xx_nand_controller_s
uint32_t addr;
uint32_t data;
uint32_t nfstat;
} s3c24xx_nand_controller_t;
};
/* Default to using the un-translated NAND register based address */
#undef S3C2410_NFREG
@ -48,7 +48,7 @@ typedef struct s3c24xx_nand_controller_s
#define S3C24XX_DEVICE_COMMAND() \
COMMAND_HELPER(s3c24xx_nand_device_command, \
struct nand_device_s *nand, \
s3c24xx_nand_controller_t **info)
struct s3c24xx_nand_controller **info)
S3C24XX_DEVICE_COMMAND();