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arm926ejs: retire cp15 commands, handled by mrc/mcr. 

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Øyvind Harboe 2009-10-26 14:08:43 +01:00
parent b8b1353dd7
commit eeb4276deb
5 changed files with 3 additions and 76 deletions
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7
doc/openocd.texi
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@ -5704,13 +5704,6 @@ they are not built from ARM926ej-s designs.
Print information about the caches found.
@end deffn
@deffn Command {arm926ejs cp15} opcode1 opcode2 CRn CRm regnum [value]
Accesses cp15 register @var{regnum} using
@var{opcode1}, @var{opcode2}, @var{CRn}, and @var{CRm}.
If a @var{value} is provided, that value is written to that register.
Else that register is read and displayed.
@end deffn
@subsection ARM966E specific commands
@cindex ARM966E

66
src/target/arm926ejs.c
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@ -713,67 +713,6 @@ static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
return arm926ejs_init_arch_info(target, arm926ejs, target->tap);
}
COMMAND_HANDLER(arm926ejs_handle_cp15_command)
{
int retval;
struct target *target = get_current_target(CMD_CTX);
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
int opcode_1;
int opcode_2;
int CRn;
int CRm;
if ((CMD_ARGC < 4) || (CMD_ARGC > 5))
{
command_print(CMD_CTX, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
return ERROR_OK;
}
COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], opcode_1);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], opcode_2);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], CRn);
COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], CRm);
retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED)
{
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
if (CMD_ARGC == 4)
{
uint32_t value;
if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
{
command_print(CMD_CTX, "couldn't access register");
return ERROR_OK;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
}
command_print(CMD_CTX, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
}
else
{
uint32_t value;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[4], value);
if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
{
command_print(CMD_CTX, "couldn't access register");
return ERROR_OK;
}
command_print(CMD_CTX, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
}
return ERROR_OK;
}
COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
{
int retval;
@ -829,11 +768,6 @@ int arm926ejs_register_commands(struct command_context *cmd_ctx)
NULL, COMMAND_ANY,
"arm926ejs specific commands");
register_command(cmd_ctx, arm926ejs_cmd, "cp15",
arm926ejs_handle_cp15_command, COMMAND_EXEC,
"display/modify cp15 register "
"<opcode_1> <opcode_2> <CRn> <CRm> [value]");
register_command(cmd_ctx, arm926ejs_cmd, "cache_info",
arm926ejs_handle_cache_info_command, COMMAND_EXEC,
"display information about target caches");

2
tcl/board/dm355evm.cfg
View File

@ -182,7 +182,7 @@ proc dm355evm_init {} {
########################
# turn on icache - set I bit in cp15 register c1
arm926ejs cp15 0 0 1 0 0x00051078
mcr 0 0 1 0 0x00051078
}
# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.

2
tcl/board/openrd.cfg
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@ -29,7 +29,7 @@ proc openrd_init { } {
jtag_reset 0 0
wait_halt
arm926ejs cp15 0 0 1 0 0x00052078
mcr 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x37543000 # Dunit Control Low Register

2
tcl/board/sheevaplug.cfg
View File

@ -29,7 +29,7 @@ proc sheevaplug_init { } {
jtag_reset 0 0
wait_halt
arm926ejs cp15 0 0 1 0 0x00052078
mcr 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 # Dunit Control Low Register