tcl/stm32l5x|u5x: refactor common tcl code
both stm32l5x and stm32u5x configs are almost identical except clock config. while at there rename target procs to avoid issues with JTAG daisy chaining. Change-Id: Ibbb1dfeb91a7f8d5d45744cf57dca2877f60e0c5 Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6596 Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins
This commit is contained in:
Tarek BOCHKATI
Antonio Borneo
parent
57c1e49180
commit
f583f338b0
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@ -1,10 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32l5x family
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# stm32l5x devices support both JTAG and SWD transports.
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#
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# stm32l5 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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@ -14,78 +12,10 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME stm32l5x
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}
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set _ENDIAN little
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source [find target/stm32x5x_common.cfg]
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0438
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# RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
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# Corresponds to Cortex®-M33 JTAG debug port ID code
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set _CPUTAPID 0x0ba04477
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} {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x0be12477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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# use non-secure RAM by default
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# create sec/ns flash and otp memories (sizes will be probed)
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flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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proc is_secure {} {
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# read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
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set DSCSR [mrw 0xE000EE08]
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return [expr {($DSCSR & (1 << 16)) != 0}]
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}
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proc clock_config_110_mhz {} {
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set offset [expr {[is_secure] ? 0x10000000 : 0}]
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proc stm32l5x_clock_config {} {
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set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
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# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
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# RCC_APB1ENR1 = PWREN
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mww [expr {0x40021058 + $offset}] 0x10000000
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@ -111,90 +41,8 @@ proc clock_config_110_mhz {} {
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while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
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}
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proc ahb_ap_non_secure_access {} {
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# SPROT=1=Non Secure access, Priv=1
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[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
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}
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proc ahb_ap_secure_access {} {
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# SPROT=0=Secure access, Priv=1
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[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
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}
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$_TARGETNAME configure -event reset-init {
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clock_config_110_mhz
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stm32l5x_clock_config
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 480
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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mmw 0xE0044004 0x00000006 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0044008 0x00001800 0
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}
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$_TARGETNAME configure -event halted {
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set secure [is_secure]
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if {$secure} {
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set secure_str "Secure"
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ahb_ap_secure_access
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} else {
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set secure_str "Non-Secure"
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ahb_ap_non_secure_access
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}
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# print the secure state only when it changes
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set _TARGETNAME [target current]
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global $_TARGETNAME.secure
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if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
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echo "CPU in $secure_str state"
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# update saved security state
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set $_TARGETNAME.secure $secure
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}
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}
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$_TARGETNAME configure -event gdb-flash-erase-start {
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set use_secure_workarea 0
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# check if FLASH_OPTR.TZEN is enabled
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set FLASH_OPTR [mrw 0x40022040]
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if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
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echo "TZEN option bit disabled"
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ahb_ap_non_secure_access
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} {
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ahb_ap_secure_access
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echo "TZEN option bit enabled"
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# check if FLASH_OPTR.RDP is not Level 0.5
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if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
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set use_secure_workarea 1
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}
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}
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set workarea_addr [$_TARGETNAME cget -work-area-phys]
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echo "workarea_addr $workarea_addr"
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if {$use_secure_workarea} {
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set workarea_addr [expr {$workarea_addr | 0x10000000}]
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} {
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set workarea_addr [expr {$workarea_addr & ~0x10000000}]
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}
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$_TARGETNAME configure -work-area-phys $workarea_addr
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0044004 0x00000020 0
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}
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@ -1,10 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# script for stm32u5x family
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# stm32u5x devices support both JTAG and SWD transports.
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#
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# stm32u5 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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@ -14,78 +12,10 @@ if { [info exists CHIPNAME] } {
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set _CHIPNAME stm32u5x
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}
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set _ENDIAN little
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source [find target/stm32x5x_common.cfg]
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0438
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# RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
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# Corresponds to Cortex®-M33 JTAG debug port ID code
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set _CPUTAPID 0x0ba04477
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} {
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# SWD IDCODE (single drop, arm)
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set _CPUTAPID 0x0be12477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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# use non-secure RAM by default
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# create sec/ns flash and otp memories (sizes will be probed)
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flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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# the safe side.
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#
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# Note that there is a pretty wide band where things are
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# more or less stable, see http://openocd.zylin.com/#/c/3366/
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adapter speed 500
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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proc is_secure {} {
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# read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
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set DSCSR [mrw 0xE000EE08]
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return [expr {($DSCSR & (1 << 16)) != 0}]
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}
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proc clock_config_160_mhz {} {
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set offset [expr {[is_secure] ? 0x10000000 : 0}]
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proc stm32u5x_clock_config {} {
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set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
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# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
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# Enable voltage range 1 for frequency above 100 Mhz
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@ -117,91 +47,8 @@ proc clock_config_160_mhz {} {
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while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
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}
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proc ahb_ap_non_secure_access {} {
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# SPROT=1=Non Secure access, Priv=1
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[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
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}
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proc ahb_ap_secure_access {} {
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# SPROT=0=Secure access, Priv=1
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[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
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}
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$_TARGETNAME configure -event reset-init {
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clock_config_160_mhz
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stm32u5x_clock_config
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# Boost JTAG frequency
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adapter speed 4000
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}
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$_TARGETNAME configure -event reset-start {
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# Reset clock is MSI (4 MHz)
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adapter speed 480
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}
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$_TARGETNAME configure -event examine-end {
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
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mmw 0xE0044004 0x00000006 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0044008 0x00001800 0
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}
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$_TARGETNAME configure -event halted {
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set secure [is_secure]
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if {$secure} {
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set secure_str "Secure"
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ahb_ap_secure_access
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} else {
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set secure_str "Non-Secure"
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ahb_ap_non_secure_access
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}
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# print the secure state only when it changes
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set _TARGETNAME [target current]
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global $_TARGETNAME.secure
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if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
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echo "CPU in $secure_str state"
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# update saved security state
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set $_TARGETNAME.secure $secure
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}
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}
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$_TARGETNAME configure -event gdb-flash-erase-start {
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set use_secure_workarea 0
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# check if FLASH_OPTR.TZEN is enabled
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set FLASH_OPTR [mrw 0x40022040]
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if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
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echo "TZEN option bit disabled"
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ahb_ap_non_secure_access
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} else {
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ahb_ap_secure_access
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echo "TZEN option bit enabled"
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# check if FLASH_OPTR.RDP is not Level 0.5
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if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
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set use_secure_workarea 1
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}
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}
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set _TARGETNAME [target current]
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set workarea_addr [$_TARGETNAME cget -work-area-phys]
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echo "workarea_addr $workarea_addr"
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if {$use_secure_workarea} {
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set workarea_addr [expr {$workarea_addr | 0x10000000}]
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} else {
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set workarea_addr [expr {$workarea_addr & ~0x10000000}]
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}
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$_TARGETNAME configure -work-area-phys $workarea_addr
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
|
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# change this value accordingly to configure trace pins
|
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# assignment
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mmw 0xE0044004 0x00000020 0
|
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}
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|
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@ -0,0 +1,154 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
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# common script for stm32l5x and stm32u5x families
|
||||
|
||||
# Work-area is a space in RAM used for flash programming
|
||||
# By default use 64kB
|
||||
if { [info exists WORKAREASIZE] } {
|
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set _WORKAREASIZE $WORKAREASIZE
|
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} else {
|
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set _WORKAREASIZE 0x10000
|
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}
|
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|
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#jtag scan chain
|
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if { [info exists CPUTAPID] } {
|
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set _CPUTAPID $CPUTAPID
|
||||
} else {
|
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if { [using_jtag] } {
|
||||
# STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
|
||||
# STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
|
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# Corresponds to Cortex®-M33 JTAG debug port ID code
|
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set _CPUTAPID 0x0ba04477
|
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} {
|
||||
# SWD IDCODE (single drop, arm)
|
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set _CPUTAPID 0x0be12477
|
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}
|
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}
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
||||
|
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if {[using_jtag]} {
|
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jtag newtap $_CHIPNAME bs -irlen 5
|
||||
}
|
||||
|
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set _TARGETNAME $_CHIPNAME.cpu
|
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target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
|
||||
|
||||
# use non-secure RAM by default
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
# create sec/ns flash and otp memories (sizes will be probed)
|
||||
flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
|
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flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
|
||||
flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
|
||||
|
||||
# Common knowledge tells JTAG speed should be <= F_CPU/6.
|
||||
# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
|
||||
# the safe side.
|
||||
#
|
||||
# Note that there is a pretty wide band where things are
|
||||
# more or less stable, see http://review.openocd.org/3366
|
||||
adapter speed 500
|
||||
|
||||
adapter srst delay 100
|
||||
if {[using_jtag]} {
|
||||
jtag_ntrst_delay 100
|
||||
}
|
||||
|
||||
reset_config srst_nogate
|
||||
|
||||
if {![using_hla]} {
|
||||
# if srst is not fitted use SYSRESETREQ to
|
||||
# perform a soft reset
|
||||
cortex_m reset_config sysresetreq
|
||||
}
|
||||
|
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proc stm32x5x_is_secure {} {
|
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# read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)
|
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set DSCSR [mrw 0xE000EE08]
|
||||
return [expr {($DSCSR & (1 << 16)) != 0}]
|
||||
}
|
||||
|
||||
proc stm32x5x_ahb_ap_non_secure_access {} {
|
||||
# SPROT=1=Non Secure access, Priv=1
|
||||
[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
|
||||
}
|
||||
|
||||
proc stm32x5x_ahb_ap_secure_access {} {
|
||||
# SPROT=0=Secure access, Priv=1
|
||||
[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-start {
|
||||
# Reset clock is MSI (4 MHz)
|
||||
adapter speed 480
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event examine-end {
|
||||
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
|
||||
mmw 0xE0044004 0x00000006 0
|
||||
|
||||
# Stop watchdog counters during halt
|
||||
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
|
||||
mmw 0xE0044008 0x00001800 0
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event halted {
|
||||
set secure [stm32x5x_is_secure]
|
||||
|
||||
if {$secure} {
|
||||
set secure_str "Secure"
|
||||
stm32x5x_ahb_ap_secure_access
|
||||
} else {
|
||||
set secure_str "Non-Secure"
|
||||
stm32x5x_ahb_ap_non_secure_access
|
||||
}
|
||||
|
||||
# print the secure state only when it changes
|
||||
set _TARGETNAME [target current]
|
||||
global $_TARGETNAME.secure
|
||||
|
||||
if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
|
||||
echo "CPU in $secure_str state"
|
||||
# update saved security state
|
||||
set $_TARGETNAME.secure $secure
|
||||
}
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event gdb-flash-erase-start {
|
||||
set use_secure_workarea 0
|
||||
# check if FLASH_OPTR.TZEN is enabled
|
||||
set FLASH_OPTR [mrw 0x40022040]
|
||||
if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
|
||||
echo "TZEN option bit disabled"
|
||||
stm32x5x_ahb_ap_non_secure_access
|
||||
} else {
|
||||
stm32x5x_ahb_ap_secure_access
|
||||
echo "TZEN option bit enabled"
|
||||
|
||||
# check if FLASH_OPTR.RDP is not Level 0.5
|
||||
if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
|
||||
set use_secure_workarea 1
|
||||
}
|
||||
}
|
||||
|
||||
set _TARGETNAME [target current]
|
||||
set workarea_addr [$_TARGETNAME cget -work-area-phys]
|
||||
echo "workarea_addr $workarea_addr"
|
||||
|
||||
if {$use_secure_workarea} {
|
||||
set workarea_addr [expr {$workarea_addr | 0x10000000}]
|
||||
} else {
|
||||
set workarea_addr [expr {$workarea_addr & ~0x10000000}]
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-phys $workarea_addr
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event trace-config {
|
||||
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
|
||||
# change this value accordingly to configure trace pins
|
||||
# assignment
|
||||
mmw 0xE0044004 0x00000020 0
|
||||
}
|
||||
Loading…
Reference in New Issue