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ARM: "armv4_5" command prefix becomes "arm" 

Rename the "armv4_5" command prefix to straight "arm" so it makes
more sense for newer cores.  Add a simple compatibility script.

Make sure all the commands give the same "not an ARM" diagnostic
message (and fail properly) when called against non-ARM targets.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell 2009-11-16 16:36:09 -08:00
parent 7c393679c0
commit f86137066a
9 changed files with 31 additions and 22 deletions
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2
NEWS
View File

@ -8,6 +8,8 @@ JTAG Layer:
Boundary Scan:
Target Layer:
ARM
- renamed "armv4_5" command prefix as "arm"
ARM11
- Preliminary ETM and ETB hookup
- accelerated "flash erase_check"

14
doc/openocd.texi
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@ -5515,16 +5515,14 @@ Reports whether the capture clock is locked or not.
@end deffn
@section ARMv4 and ARMv5 Architecture
@cindex ARMv4
@cindex ARMv5
@section Generic ARM
@cindex ARM
These commands are specific to ARM architecture v4 and v5,
including all ARM7 or ARM9 systems and Intel XScale.
These commands should be available on all ARM processors.
They are available in addition to other core-specific
commands that may be available.
@deffn Command {armv4_5 core_state} [@option{arm}|@option{thumb}]
@deffn Command {arm core_state} [@option{arm}|@option{thumb}]
Displays the core_state, optionally changing it to process
either @option{arm} or @option{thumb} instructions.
The target may later be resumed in the currently set core_state.
@ -5532,7 +5530,7 @@ The target may later be resumed in the currently set core_state.
that is not currently supported in OpenOCD.)
@end deffn
@deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
@deffn Command {arm disassemble} address [count [@option{thumb}]]
@cindex disassemble
Disassembles @var{count} instructions starting at @var{address}.
If @var{count} is not specified, a single instruction is disassembled.
@ -5543,7 +5541,7 @@ else ARM (32-bit) instructions are used.
those instructions are not currently understood by OpenOCD.)
@end deffn
@deffn Command {armv4_5 reg}
@deffn Command {arm reg}
Display a table of all banked core registers, fetching the current value from every
core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
register value.

9
src/helper/startup.tcl
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@ -142,6 +142,15 @@ proc ocd_gdb_restart {target_id} {
reset halt
}
#########
# Temporary migration aid. May be removed starting in January 2011.
proc armv4_5 params {
echo "DEPRECATED! use 'arm $params' not 'armv4_5 $params'"
arm $params
}
#########
# This reset logic may be overridden by board/target/... scripts as needed
# to provide a reset that, if possible, is close to a power-up reset.

18
src/target/armv4_5.c
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@ -363,10 +363,10 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
if (!is_arm(armv4_5))
{
command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
return ERROR_OK;
command_print(cmd_ctx, "current target isn't an ARM");
return ERROR_FAIL;
}
if (target->state != TARGET_HALTED)
@ -412,10 +412,10 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
struct target *target = get_current_target(cmd_ctx);
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
if (!is_arm(armv4_5))
{
command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
return ERROR_OK;
command_print(cmd_ctx, "current target isn't an ARM");
return ERROR_FAIL;
}
if (argc > 0)
@ -471,7 +471,7 @@ COMMAND_HANDLER(handle_armv4_5_disassemble_command)
default:
usage:
command_print(cmd_ctx,
"usage: armv4_5 disassemble <address> [<count> ['thumb']]");
"usage: arm disassemble <address> [<count> ['thumb']]");
count = 0;
retval = ERROR_FAIL;
}
@ -510,9 +510,9 @@ int armv4_5_register_commands(struct command_context *cmd_ctx)
{
struct command *armv4_5_cmd;
armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5",
armv4_5_cmd = register_command(cmd_ctx, NULL, "arm",
NULL, COMMAND_ANY,
"armv4/5 specific commands");
"generic ARM commands");
register_command(cmd_ctx, armv4_5_cmd, "reg",
handle_armv4_5_reg_command, COMMAND_EXEC,

2
tcl/board/mini2440.cfg
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@ -292,7 +292,7 @@ proc load_uboot { } {
proc s {} {
step
reg
armv4_5 disassemble 0x33F80068 0x10
arm disassemble 0x33F80068 0x10
}
proc help_2440 {} {

2
tcl/target/lpc1768.cfg
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@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-a
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
armv4_5 core_state arm
arm core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
# mwb 0xE01FC040 0x01
mwb 0xE000ED08 0x00

2
tcl/target/lpc2148.cfg
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@ -39,7 +39,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-a
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
armv4_5 core_state arm
arm core_state arm
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,

2
tcl/target/lpc2378.cfg
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@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x8000 -work-a
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
armv4_5 core_state arm
arm core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
mwb 0xE01FC040 0x01
}

2
tcl/target/lpc2478.cfg
View File

@ -35,7 +35,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work-
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
armv4_5 core_state arm
arm core_state arm
# Do not remap 0x0000-0x0020 to anything but the Flash
mwb 0xE01FC040 0x01
}