Support for Freescale LS102x SAP
The SAP in LS102x SoC's from Freescale is able to read and write to all physical memory locations, independently of CPU cores and DAP. This implementation is 100% based on reverse-engineering of JTAG communication with an LS1021A SAP using a JTAG debugger with SAP support. And as such, this code is for now "works-for-me", pending verification by other OpenOCD users, or even better, actual information from Freescale on the SAP interface. Change-Id: Ibb30945e017894da5c402f9f633fc513bed4e68c Signed-off-by: Esben Haabendal <esben@haabendal.dk> Reviewed-on: http://openocd.zylin.com/3096 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Esben Haabendal
Paul Fertser
parent
406f4d1c68
commit
f906c65fed
2
README
2
README
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@ -119,7 +119,7 @@ Wiggler, XDS100v2, Xverve.
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Debug targets
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-------------
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ARM11, ARM7, ARM9, AVR32, Cortex-A, Cortex-R, Cortex-M,
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ARM11, ARM7, ARM9, AVR32, Cortex-A, Cortex-R, Cortex-M, LS102x-SAP,
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Feroceon/Dragonite, DSP563xx, DSP5680xx, FA526, MIPS EJTAG, NDS32,
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XScale, Intel Quark.
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@ -4059,6 +4059,8 @@ compact Thumb2 instruction set.
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not a CPU type. It is based on the ARMv5 architecture.
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@item @code{openrisc} -- this is an OpenRISC 1000 core.
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The current implementation supports three JTAG TAP cores:
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@item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
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allowing access to physical memory addresses independently of CPU cores.
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@itemize @minus
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@item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag})
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@item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
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@ -82,7 +82,8 @@ ARMV7_SRC = \
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armv7m_trace.c \
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cortex_m.c \
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armv7a.c \
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cortex_a.c
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cortex_a.c \
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ls1_sap.c
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ARM_DEBUG_SRC = \
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arm_dpm.c \
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@ -0,0 +1,243 @@
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/***************************************************************************
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* Copyright (C) 2015 by Esben Haabendal *
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* eha@deif.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "target.h"
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#include "target_type.h"
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#include <jtag/jtag.h>
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struct ls1_sap {
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struct jtag_tap *tap;
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};
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static int ls1_sap_target_create(struct target *target, Jim_Interp *interp)
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{
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struct ls1_sap *ls1_sap = calloc(1, sizeof(struct ls1_sap));
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ls1_sap->tap = target->tap;
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target->arch_info = ls1_sap;
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return ERROR_OK;
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}
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static int ls1_sap_init_target(struct command_context *cmd_ctx, struct target *target)
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{
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LOG_DEBUG("%s", __func__);
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return ERROR_OK;
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}
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static int ls1_sap_arch_state(struct target *target)
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{
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LOG_DEBUG("%s", __func__);
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return ERROR_OK;
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}
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static int ls1_sap_poll(struct target *target)
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{
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if ((target->state == TARGET_UNKNOWN) ||
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(target->state == TARGET_RUNNING) ||
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(target->state == TARGET_DEBUG_RUNNING))
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target->state = TARGET_HALTED;
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return ERROR_OK;
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}
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static int ls1_sap_halt(struct target *target)
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{
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LOG_DEBUG("%s", __func__);
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return ERROR_OK;
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}
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static int ls1_sap_resume(struct target *target, int current, uint32_t address,
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int handle_breakpoints, int debug_execution)
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{
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LOG_DEBUG("%s", __func__);
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return ERROR_OK;
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}
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static int ls1_sap_step(struct target *target, int current, uint32_t address,
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int handle_breakpoints)
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{
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LOG_DEBUG("%s", __func__);
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return ERROR_OK;
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}
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static int ls1_sap_assert_reset(struct target *target)
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{
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target->state = TARGET_RESET;
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LOG_DEBUG("%s", __func__);
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return ERROR_OK;
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}
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static int ls1_sap_deassert_reset(struct target *target)
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{
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target->state = TARGET_RUNNING;
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LOG_DEBUG("%s", __func__);
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return ERROR_OK;
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}
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static void ls1_sap_set_instr(struct jtag_tap *tap, uint32_t new_instr)
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{
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struct scan_field field;
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if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) == new_instr)
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return;
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field.num_bits = tap->ir_length;
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uint8_t *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
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field.out_value = t;
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buf_set_u32(t, 0, field.num_bits, new_instr);
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field.in_value = NULL;
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jtag_add_ir_scan(tap, &field, TAP_IDLE);
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free(t);
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}
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static void ls1_sap_set_addr_high(struct jtag_tap *tap, uint16_t addr_high)
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{
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struct scan_field field;
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uint8_t buf[2];
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ls1_sap_set_instr(tap, 0x21);
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field.num_bits = 16;
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field.out_value = buf;
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buf_set_u32(buf, 0, 16, addr_high);
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field.in_value = NULL;
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field.check_value = NULL;
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field.check_mask = NULL;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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}
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static void ls1_sap_memory_cmd(struct jtag_tap *tap, uint32_t address,
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int32_t size, int read)
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{
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struct scan_field field;
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uint8_t cmd[8];
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ls1_sap_set_instr(tap, 0x24);
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field.num_bits = 64;
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field.out_value = cmd;
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buf_set_u64(cmd, 0, 9, 0);
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buf_set_u64(cmd, 9, 3, size);
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buf_set_u64(cmd, 12, 1, !!read);
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buf_set_u64(cmd, 13, 3, 0);
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buf_set_u64(cmd, 16, 32, address);
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buf_set_u64(cmd, 48, 16, 0);
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field.in_value = NULL;
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field.check_value = NULL;
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field.check_mask = NULL;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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}
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static void ls1_sap_memory_read(struct jtag_tap *tap, uint32_t size,
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uint8_t *value)
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{
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struct scan_field field;
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ls1_sap_set_instr(tap, 0x25);
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field.num_bits = 8 * size;
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field.out_value = NULL;
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field.in_value = value;
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field.check_value = NULL;
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field.check_mask = NULL;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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}
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static void ls1_sap_memory_write(struct jtag_tap *tap, uint32_t size,
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const uint8_t *value)
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{
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struct scan_field field;
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ls1_sap_set_instr(tap, 0x25);
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field.num_bits = 8 * size;
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field.out_value = value;
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field.in_value = NULL;
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field.check_value = NULL;
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field.check_mask = NULL;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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}
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static int ls1_sap_read_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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LOG_DEBUG("Reading memory at physical address 0x%" PRIx32
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"; size %" PRId32 "; count %" PRId32, address, size, count);
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if (count == 0 || buffer == NULL)
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return ERROR_COMMAND_SYNTAX_ERROR;
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ls1_sap_set_addr_high(target->tap, 0);
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while (count--) {
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ls1_sap_memory_cmd(target->tap, address, size, 1);
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ls1_sap_memory_read(target->tap, size, buffer);
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address += size;
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buffer += size;
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}
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return jtag_execute_queue();
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}
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static int ls1_sap_write_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count,
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const uint8_t *buffer)
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{
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LOG_DEBUG("Writing memory at physical address 0x%" PRIx32
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"; size %" PRId32 "; count %" PRId32, address, size, count);
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if (count == 0 || buffer == NULL)
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return ERROR_COMMAND_SYNTAX_ERROR;
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ls1_sap_set_addr_high(target->tap, 0);
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while (count--) {
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ls1_sap_memory_cmd(target->tap, address, size, 0);
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ls1_sap_memory_write(target->tap, size, buffer);
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address += size;
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buffer += size;
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}
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return jtag_execute_queue();
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}
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struct target_type ls1_sap_target = {
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.name = "ls1_sap",
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.target_create = ls1_sap_target_create,
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.init_target = ls1_sap_init_target,
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.poll = ls1_sap_poll,
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.arch_state = ls1_sap_arch_state,
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.halt = ls1_sap_halt,
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.resume = ls1_sap_resume,
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.step = ls1_sap_step,
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.assert_reset = ls1_sap_assert_reset,
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.deassert_reset = ls1_sap_deassert_reset,
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.read_memory = ls1_sap_read_memory,
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.write_memory = ls1_sap_write_memory,
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};
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@ -90,6 +90,7 @@ extern struct target_type cortexm_target;
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extern struct target_type cortexa_target;
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extern struct target_type cortexr4_target;
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extern struct target_type arm11_target;
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extern struct target_type ls1_sap_target;
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extern struct target_type mips_m4k_target;
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extern struct target_type avr_target;
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extern struct target_type dsp563xx_target;
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@ -120,6 +121,7 @@ static struct target_type *target_types[] = {
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&cortexa_target,
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&cortexr4_target,
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&arm11_target,
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&ls1_sap_target,
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&mips_m4k_target,
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&avr_target,
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&dsp563xx_target,
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