mips32: add gdb target description support
This commit is inspired by
commit 1255b18fc6
Author: Spencer Oliver <spen@spen-soft.co.uk>
Date: Fri Sep 13 09:44:36 2013 +0100
armv7m: add gdb target description support
Change-Id: I75c3971fd0599d34ed49fb73975378b57f2a4af0
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
CC: Spencer Oliver <spen@spen-soft.co.uk>
CC: Oleksij Rempel <linux@rempel-privat.de>
CC: Paul Fertser <fercerpav@gmail.com>
CC: Gregory Fong <gregory.0xf0@gmail.com>
Reviewed-on: http://openocd.zylin.com/1972
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
This commit is contained in:
Antony Pavlov
Andreas Fritiofson
parent
3f447bb8dd
commit
fd43be0726
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@ -39,67 +39,134 @@ static const char *mips_isa_strings[] = {
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"MIPS32", "MIPS16e"
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};
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#define MIPS32_GDB_DUMMY_FP_REG 1
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/*
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* GDB registers
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* based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu}.xml
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*/
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static const struct {
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unsigned id;
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const char *name;
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} mips32_regs[MIPS32NUMCOREREGS] = {
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{ 0, "zero", },
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{ 1, "at", },
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{ 2, "v0", },
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{ 3, "v1", },
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{ 4, "a0", },
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{ 5, "a1", },
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{ 6, "a2", },
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{ 7, "a3", },
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{ 8, "t0", },
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{ 9, "t1", },
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{ 10, "t2", },
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{ 11, "t3", },
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{ 12, "t4", },
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{ 13, "t5", },
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{ 14, "t6", },
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{ 15, "t7", },
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{ 16, "s0", },
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{ 17, "s1", },
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{ 18, "s2", },
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{ 19, "s3", },
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{ 20, "s4", },
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{ 21, "s5", },
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{ 22, "s6", },
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{ 23, "s7", },
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{ 24, "t8", },
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{ 25, "t9", },
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{ 26, "k0", },
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{ 27, "k1", },
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{ 28, "gp", },
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{ 29, "sp", },
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{ 30, "fp", },
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{ 31, "ra", },
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enum reg_type type;
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const char *group;
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const char *feature;
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int flag;
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} mips32_regs[] = {
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{ 0, "r0", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 1, "r1", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 2, "r2", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 3, "r3", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 4, "r4", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 5, "r5", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 6, "r6", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 7, "r7", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 8, "r8", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 9, "r9", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 10, "r10", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 11, "r11", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 12, "r12", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 13, "r13", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 14, "r14", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 15, "r15", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 16, "r16", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 17, "r17", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 18, "r18", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 19, "r19", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 20, "r20", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 21, "r21", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 22, "r22", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 23, "r23", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 24, "r24", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 25, "r25", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 26, "r26", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 27, "r27", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 28, "r28", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 29, "r29", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 30, "r30", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 31, "r31", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 32, "status", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
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{ 33, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 34, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 35, "badvaddr", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
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{ 36, "cause", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
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{ 37, "pc", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
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{ 32, "status", },
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{ 33, "lo", },
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{ 34, "hi", },
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{ 35, "badvaddr", },
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{ 36, "cause", },
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{ 37, "pc" },
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{ 38, "f0", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 39, "f1", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 40, "f2", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 41, "f3", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 42, "f4", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 43, "f5", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 44, "f6", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 45, "f7", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 46, "f8", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 47, "f9", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 48, "f10", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 49, "f11", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 50, "f12", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 51, "f13", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 52, "f14", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 53, "f15", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 54, "f16", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 55, "f17", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 56, "f18", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 57, "f19", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 58, "f20", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 59, "f21", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 60, "f22", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 61, "f23", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 62, "f24", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 63, "f25", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 64, "f26", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 65, "f27", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 66, "f28", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 67, "f29", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 68, "f30", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 69, "f31", REG_TYPE_IEEE_SINGLE, NULL,
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 70, "fcsr", REG_TYPE_INT, "float",
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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{ 71, "fir", REG_TYPE_INT, "float",
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"org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
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};
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/* number of mips dummy fp regs fp0 - fp31 + fsr and fir
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* we also add 18 unknown registers to handle gdb requests */
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#define MIPS32NUMFPREGS (34 + 18)
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#define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs)
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static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
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static struct reg mips32_gdb_dummy_fp_reg = {
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.name = "GDB dummy floating-point register",
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.value = mips32_gdb_dummy_fp_value,
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.dirty = 0,
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.valid = 1,
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.size = 32,
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.arch_info = NULL,
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};
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static int mips32_get_core_reg(struct reg *reg)
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{
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int retval;
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@ -138,7 +205,7 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target_to_mips32(target);
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if (num >= MIPS32NUMCOREREGS)
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if (num >= MIPS32_NUM_REGS)
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return ERROR_COMMAND_SYNTAX_ERROR;
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reg_value = mips32->core_regs[num];
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@ -156,7 +223,7 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target_to_mips32(target);
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if (num >= MIPS32NUMCOREREGS)
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if (num >= MIPS32_NUM_REGS)
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return ERROR_COMMAND_SYNTAX_ERROR;
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reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
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@ -176,16 +243,12 @@ int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
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unsigned int i;
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/* include floating point registers */
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*reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
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*reg_list_size = MIPS32_NUM_REGS;
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*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
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for (i = 0; i < MIPS32NUMCOREREGS; i++)
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for (i = 0; i < MIPS32_NUM_REGS; i++)
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(*reg_list)[i] = &mips32->core_cache->reg_list[i];
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/* add dummy floating points regs */
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for (i = MIPS32NUMCOREREGS; i < (MIPS32NUMCOREREGS + MIPS32NUMFPREGS); i++)
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(*reg_list)[i] = &mips32_gdb_dummy_fp_reg;
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return ERROR_OK;
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}
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@ -200,7 +263,7 @@ int mips32_save_context(struct target *target)
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/* read core registers */
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mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
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for (i = 0; i < MIPS32NUMCOREREGS; i++) {
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for (i = 0; i < MIPS32_NUM_REGS; i++) {
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if (!mips32->core_cache->reg_list[i].valid)
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mips32->read_core_reg(target, i);
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}
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@ -216,7 +279,7 @@ int mips32_restore_context(struct target *target)
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struct mips32_common *mips32 = target_to_mips32(target);
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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for (i = 0; i < MIPS32NUMCOREREGS; i++) {
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for (i = 0; i < MIPS32_NUM_REGS; i++) {
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if (mips32->core_cache->reg_list[i].dirty)
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mips32->write_core_reg(target, i);
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}
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@ -249,15 +312,14 @@ struct reg_cache *mips32_build_reg_cache(struct target *target)
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/* get pointers to arch-specific information */
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struct mips32_common *mips32 = target_to_mips32(target);
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int num_regs = MIPS32NUMCOREREGS;
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int num_regs = MIPS32_NUM_REGS;
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struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
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struct reg_cache *cache = malloc(sizeof(struct reg_cache));
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struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
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struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
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struct reg_feature *feature;
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int i;
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register_init_dummy(&mips32_gdb_dummy_fp_reg);
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/* Build the process context cache */
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cache->name = "mips32 registers";
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cache->next = NULL;
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@ -273,11 +335,38 @@ struct reg_cache *mips32_build_reg_cache(struct target *target)
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reg_list[i].name = mips32_regs[i].name;
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reg_list[i].size = 32;
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reg_list[i].value = calloc(1, 4);
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if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) {
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reg_list[i].value = mips32_gdb_dummy_fp_value;
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reg_list[i].valid = 1;
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reg_list[i].arch_info = NULL;
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register_init_dummy(®_list[i]);
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} else {
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reg_list[i].value = calloc(1, 4);
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reg_list[i].valid = 0;
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reg_list[i].type = &mips32_reg_type;
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reg_list[i].arch_info = &arch_info[i];
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reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
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if (reg_list[i].reg_data_type)
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reg_list[i].reg_data_type->type = mips32_regs[i].type;
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else
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LOG_ERROR("unable to allocate reg type list");
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}
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reg_list[i].dirty = 0;
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reg_list[i].valid = 0;
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reg_list[i].type = &mips32_reg_type;
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reg_list[i].arch_info = &arch_info[i];
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reg_list[i].group = mips32_regs[i].group;
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reg_list[i].number = i;
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reg_list[i].exist = true;
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reg_list[i].caller_save = true; /* gdb defaults to true */
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feature = calloc(1, sizeof(struct reg_feature));
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if (feature) {
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feature->name = mips32_regs[i].feature;
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reg_list[i].feature = feature;
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} else
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LOG_ERROR("unable to allocate feature list");
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}
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return cache;
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@ -345,7 +434,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
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struct mips32_algorithm *mips32_algorithm_info = arch_info;
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enum mips32_isa_mode isa_mode = mips32->isa_mode;
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uint32_t context[MIPS32NUMCOREREGS];
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uint32_t context[MIPS32_NUM_REGS];
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int retval = ERROR_OK;
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LOG_DEBUG("Running algorithm");
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@ -364,7 +453,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
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}
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/* refresh core register cache */
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for (unsigned int i = 0; i < MIPS32NUMCOREREGS; i++) {
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for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) {
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if (!mips32->core_cache->reg_list[i].valid)
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||||
mips32->read_core_reg(target, i);
|
||||
context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
|
||||
|
|
@ -429,7 +518,7 @@ int mips32_run_algorithm(struct target *target, int num_mem_params,
|
|||
}
|
||||
|
||||
/* restore everything we saved before */
|
||||
for (unsigned int i = 0; i < MIPS32NUMCOREREGS; i++) {
|
||||
for (unsigned int i = 0; i < MIPS32_NUM_REGS; i++) {
|
||||
uint32_t regvalue;
|
||||
regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
|
||||
if (regvalue != context[i]) {
|
||||
|
|
@ -661,10 +750,10 @@ int mips32_checksum_memory(struct target *target, uint32_t address,
|
|||
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
|
||||
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
|
||||
|
||||
init_reg_param(®_params[0], "a0", 32, PARAM_IN_OUT);
|
||||
init_reg_param(®_params[0], "r4", 32, PARAM_IN_OUT);
|
||||
buf_set_u32(reg_params[0].value, 0, 32, address);
|
||||
|
||||
init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
|
||||
init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
|
||||
buf_set_u32(reg_params[1].value, 0, 32, count);
|
||||
|
||||
int timeout = 20000 * (1 + (count / (1024 * 1024)));
|
||||
|
|
@ -716,13 +805,13 @@ int mips32_blank_check_memory(struct target *target,
|
|||
mips32_info.common_magic = MIPS32_COMMON_MAGIC;
|
||||
mips32_info.isa_mode = MIPS32_ISA_MIPS32;
|
||||
|
||||
init_reg_param(®_params[0], "a0", 32, PARAM_OUT);
|
||||
init_reg_param(®_params[0], "r4", 32, PARAM_OUT);
|
||||
buf_set_u32(reg_params[0].value, 0, 32, address);
|
||||
|
||||
init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
|
||||
init_reg_param(®_params[1], "r5", 32, PARAM_OUT);
|
||||
buf_set_u32(reg_params[1].value, 0, 32, count);
|
||||
|
||||
init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT);
|
||||
init_reg_param(®_params[2], "r6", 32, PARAM_IN_OUT);
|
||||
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
|
||||
|
||||
int retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
|
||||
|
|
|
|||
|
|
@ -66,6 +66,7 @@
|
|||
/* offsets into mips32 core register cache */
|
||||
enum {
|
||||
MIPS32_PC = 37,
|
||||
MIPS32_FIR = 71,
|
||||
MIPS32NUMCOREREGS
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue