- added support for Intel/Marvel PXA27x (XScale) targets
- added support for scans coming from or ending in Shift-DR or Shift-IR to bitbang code (required for XScale debugging) - cleaned up errror handlers. only use when there's a catchable error - fix segfault when etm was configured without a valid driver git-svn-id: svn://svn.berlios.de/openocd/trunk@176 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
parent
ee01d04908
commit
ffb51c23fd
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@ -132,21 +132,35 @@ void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
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enum tap_state saved_end_state = end_state;
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int bit_cnt;
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if (ir_scan)
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bitbang_end_state(TAP_SI);
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else
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bitbang_end_state(TAP_SD);
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if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
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{
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if (ir_scan)
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bitbang_end_state(TAP_SI);
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else
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bitbang_end_state(TAP_SD);
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bitbang_state_move();
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bitbang_end_state(saved_end_state);
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bitbang_state_move();
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bitbang_end_state(saved_end_state);
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}
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for (bit_cnt = 0; bit_cnt < scan_size; bit_cnt++)
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{
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/* set TMS high on the last bit unless we want to end in TAP_SD/SI */
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int tms;
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if ((ir_scan && (end_state == TAP_SI)) ||
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(!ir_scan && (end_state == TAP_SD)))
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{
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tms = 0;
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} else {
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tms = (bit_cnt==scan_size-1) ? 1 : 0;
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}
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/* if we're just reading the scan, but don't care about the output
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* default to outputting 'low', this also makes valgrind traces more readable,
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* as it removes the dependency on an uninitialised value
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*/
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if ((type != SCAN_IN) && ((buffer[bit_cnt/8] >> (bit_cnt % 8)) & 0x1)) {
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if ((type != SCAN_IN) && ((buffer[bit_cnt/8] >> (bit_cnt % 8)) & 0x1))
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{
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bitbang_interface->write(0, (bit_cnt==scan_size-1) ? 1 : 0, 1);
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bitbang_interface->write(1, (bit_cnt==scan_size-1) ? 1 : 0, 1);
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} else {
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@ -58,6 +58,8 @@ static cmd_queue_page_t *cmd_queue_pages = NULL;
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* 3: Pause-DR
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* 4: Shift-IR
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* 5: Pause-IR
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*
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* SD->SD and SI->SI have to be caught in interface specific code
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*/
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u8 tap_move[6][6] =
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{
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@ -1086,9 +1088,6 @@ int jtag_read_buffer(u8 *buffer, scan_command_t *cmd)
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if (compare_failed)
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{
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char *captured_char = buf_to_str(captured, (num_bits > 64) ? 64 : num_bits, 16);
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char *in_check_value_char = buf_to_str(cmd->fields[i].in_check_value, (num_bits > 64) ? 64 : num_bits, 16);
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if (cmd->error_handler)
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{
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/* ask the error handler if once has been specified if this is a real problem */
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@ -1109,6 +1108,9 @@ int jtag_read_buffer(u8 *buffer, scan_command_t *cmd)
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*/
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if (compare_failed)
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{
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char *captured_char = buf_to_str(captured, (num_bits > 64) ? 64 : num_bits, 16);
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char *in_check_value_char = buf_to_str(cmd->fields[i].in_check_value, (num_bits > 64) ? 64 : num_bits, 16);
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if (cmd->fields[i].in_check_mask)
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{
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char *in_check_mask_char;
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@ -1120,10 +1122,11 @@ int jtag_read_buffer(u8 *buffer, scan_command_t *cmd)
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{
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WARNING("value captured during scan didn't pass the requested check: captured: 0x%s check_value: 0x%s", captured_char, in_check_value_char);
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}
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free(captured_char);
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free(in_check_value_char);
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}
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free(captured_char);
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free(in_check_value_char);
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}
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}
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free(captured);
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@ -59,6 +59,9 @@ extern tap_transition_t tap_transitions[16]; /* describe the TAP state diagram *
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extern enum tap_state end_state; /* finish DR scans in dr_end_state */
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extern enum tap_state cur_state; /* current TAP state */
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extern enum tap_state cmd_queue_end_state; /* finish DR scans in dr_end_state */
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extern enum tap_state cmd_queue_cur_state; /* current TAP state */
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#define TAP_MOVE(from, to) tap_move[tap_move_map[from]][tap_move_map[to]]
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typedef struct error_handler_s
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@ -846,6 +846,13 @@ int arm7_9_prepare_reset_halt(target_t *target)
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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/* poll the target, and resume if it was currently halted */
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arm7_9_poll(target);
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if (target->state == TARGET_HALTED)
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{
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arm7_9_resume(target, 1, 0x0, 0, 1);
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}
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if (arm7_9->has_vector_catch)
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{
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/* program vector catch register to catch reset vector */
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@ -104,7 +104,7 @@ int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv)
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DEBUG("caller: %s", caller);
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return ERROR_OK;
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return ERROR_JTAG_QUEUE_FAILED;
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}
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int arm9tdmi_examine_debug_reason(target_t *target)
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@ -117,7 +117,6 @@ int arm9tdmi_examine_debug_reason(target_t *target)
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if ((target->debug_reason != DBG_REASON_DBGRQ)
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&& (target->debug_reason != DBG_REASON_SINGLESTEP))
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{
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error_handler_t error_handler;
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scan_field_t fields[3];
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u8 databus[4];
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u8 instructionbus[4];
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@ -156,9 +155,7 @@ int arm9tdmi_examine_debug_reason(target_t *target)
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fields[2].in_handler_priv = NULL;
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arm_jtag_scann(&arm7_9->jtag_info, 0x1);
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error_handler.error_handler = arm9tdmi_jtag_error_handler;
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error_handler.error_handler_priv = "arm9tdmi_examine_debug_reason";
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arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, &error_handler);
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arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
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jtag_add_dr_scan(3, fields, TAP_PD, NULL);
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jtag_execute_queue();
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@ -187,7 +184,6 @@ int arm9tdmi_examine_debug_reason(target_t *target)
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/* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
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int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
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{
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error_handler_t error_handler;
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scan_field_t fields[3];
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u8 out_buf[4];
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u8 instr_buf[4];
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@ -204,10 +200,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
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jtag_add_end_state(TAP_PD);
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arm_jtag_scann(jtag_info, 0x1);
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error_handler.error_handler = arm9tdmi_jtag_error_handler;
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error_handler.error_handler_priv = "arm9tdmi_clock_out";
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 32;
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@ -271,15 +264,11 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
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int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
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{
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scan_field_t fields[3];
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error_handler_t error_handler;
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jtag_add_end_state(TAP_PD);
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arm_jtag_scann(jtag_info, 0x1);
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error_handler.error_handler = arm9tdmi_jtag_error_handler;
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error_handler.error_handler_priv = "arm9tdmi_clock_data_in_endianness";
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 32;
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@ -340,15 +329,11 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
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int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
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{
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scan_field_t fields[3];
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error_handler_t error_handler;
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jtag_add_end_state(TAP_PD);
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arm_jtag_scann(jtag_info, 0x1);
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error_handler.error_handler = arm9tdmi_jtag_error_handler;
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error_handler.error_handler_priv = "arm9tdmi_clock_data_in_endianness";
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 32;
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@ -54,26 +54,14 @@ are immediatley available.
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* *
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***************************************************************************/
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int swjdp_jtag_error_handler(u8 *in_value, void *priv)
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{
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char *caller = priv;
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DEBUG("caller: %s", caller);
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return ERROR_OK;
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}
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/* Scan out and in from target ordered u8 buffers */
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int swjdp_scan(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
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{
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scan_field_t fields[2];
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u8 out_addr_buf;
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error_handler_t error_handler;
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jtag_add_end_state(TAP_RTI);
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error_handler.error_handler = swjdp_jtag_error_handler;
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error_handler.error_handler_priv = "swjdp_scan";
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arm_jtag_set_instr(jtag_info, chain, &error_handler);
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arm_jtag_set_instr(jtag_info, chain, NULL);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 3;
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@ -108,12 +96,9 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 chain, u8 reg_addr, u8 RnW, u32 out
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scan_field_t fields[2];
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u8 out_value_buf[4];
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u8 out_addr_buf;
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error_handler_t error_handler;
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jtag_add_end_state(TAP_RTI);
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error_handler.error_handler = swjdp_jtag_error_handler;
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error_handler.error_handler_priv = "swjdp_scan_u32";
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arm_jtag_set_instr(jtag_info, chain, &error_handler);
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arm_jtag_set_instr(jtag_info, chain, NULL);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 3;
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@ -86,15 +86,6 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
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int embeddedice_write_reg(reg_t *reg, u32 value);
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int embeddedice_read_reg(reg_t *reg);
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int embeddedice_jtag_error_handler(u8 *in_value, void *priv)
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{
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char *caller = priv;
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DEBUG("caller: %s", caller);
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return ERROR_OK;
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}
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reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7_9)
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{
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reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
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@ -223,17 +214,13 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
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embeddedice_reg_t *ice_reg = reg->arch_info;
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u8 reg_addr = ice_reg->addr & 0x1f;
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scan_field_t fields[3];
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error_handler_t error_handler;
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DEBUG("%i", ice_reg->addr);
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jtag_add_end_state(TAP_RTI);
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arm_jtag_scann(ice_reg->jtag_info, 0x2);
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error_handler.error_handler = embeddedice_jtag_error_handler;
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error_handler.error_handler_priv = "embeddedice_read_reg_w_check";
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arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, &error_handler);
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arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
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fields[0].device = ice_reg->jtag_info->chain_pos;
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fields[0].num_bits = 32;
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@ -324,16 +311,12 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
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embeddedice_reg_t *ice_reg = reg->arch_info;
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u8 reg_addr = ice_reg->addr & 0x1f;
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scan_field_t fields[3];
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error_handler_t error_handler;
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DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
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jtag_add_end_state(TAP_RTI);
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arm_jtag_scann(ice_reg->jtag_info, 0x2);
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error_handler.error_handler = embeddedice_jtag_error_handler;
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error_handler.error_handler_priv = "embeddedice_write_reg";
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arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
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fields[0].device = ice_reg->jtag_info->chain_pos;
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@ -1231,6 +1231,14 @@ int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char
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}
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}
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if (!etm_capture_drivers[i])
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{
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/* no supported capture driver found, don't register an ETM */
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free(etm_ctx);
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ERROR("trace capture driver '%s' not found", args[4]);
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return ERROR_OK;
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}
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etm_ctx->target = target;
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etm_ctx->trace_data = NULL;
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etm_ctx->trace_depth = 0;
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@ -1,5 +1,5 @@
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/***************************************************************************
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* Copyright (C) 2006 by Dominic Rath *
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* Copyright (C) 2006, 2007 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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@ -34,15 +34,16 @@
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#include "binarybuffer.h"
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#include "time_support.h"
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#include "breakpoints.h"
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#include "fileio.h"
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#include <stdlib.h>
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#include <string.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <unistd.h>
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#include <errno.h>
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/* cli handling */
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int xscale_register_commands(struct command_context_s *cmd_ctx);
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@ -1197,9 +1198,6 @@ int xscale_halt(target_t *target)
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else if (target->state == TARGET_RESET)
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{
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DEBUG("target->state == TARGET_RESET");
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/* clear TRST */
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jtag_add_reset(0, -1);
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}
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else
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{
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@ -1517,22 +1515,32 @@ int xscale_assert_reset(target_t *target)
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xscale_common_t *xscale = armv4_5->arch_info;
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DEBUG("target->state: %s", target_state_strings[target->state]);
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/* select DCSR instruction (set endstate to R-T-I to ensure we don't
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* end up in T-L-R, which would reset JTAG
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*/
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jtag_add_end_state(TAP_RTI);
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xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.dcsr);
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/* if the handler isn't installed yet, we have to assert TRST, too */
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if (!xscale->handler_installed)
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{
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jtag_add_reset(1, 1);
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}
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else
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jtag_add_reset(-1, 1);
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/* set Hold reset, Halt mode and Trap Reset */
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buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
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buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
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xscale_write_dcsr(target, 1, 0);
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/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
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xscale_jtag_set_instr(xscale->jtag_info.chain_pos, 0x7f);
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jtag_execute_queue();
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/* assert reset */
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jtag_add_reset(0, 1);
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/* sleep 1ms, to be sure we fulfill any requirements */
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jtag_add_sleep(1000);
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jtag_execute_queue();
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target->state = TARGET_RESET;
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return ERROR_OK;
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}
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int xscale_deassert_reset(target_t *target)
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@ -1540,17 +1548,18 @@ int xscale_deassert_reset(target_t *target)
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armv4_5_common_t *armv4_5 = target->arch_info;
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xscale_common_t *xscale = armv4_5->arch_info;
|
||||
|
||||
FILE *binary;
|
||||
fileio_t debug_handler;
|
||||
u32 address;
|
||||
struct stat binary_stat;
|
||||
u32 binary_size;
|
||||
|
||||
u32 buffer[8];
|
||||
u32 buf_cnt;
|
||||
int i;
|
||||
int retval;
|
||||
|
||||
breakpoint_t *breakpoint = target->breakpoints;
|
||||
|
||||
DEBUG("-");
|
||||
|
||||
xscale->ibcr_available = 2;
|
||||
xscale->ibcr0_used = 0;
|
||||
xscale->ibcr1_used = 0;
|
||||
|
|
@ -1571,42 +1580,27 @@ int xscale_deassert_reset(target_t *target)
|
|||
|
||||
if (!xscale->handler_installed)
|
||||
{
|
||||
/* release TRST */
|
||||
jtag_add_reset(0, -1);
|
||||
jtag_add_sleep(100000);
|
||||
/* release SRST */
|
||||
jtag_add_reset(0, 0);
|
||||
|
||||
/* wait 300ms; 150 and 100ms were not enough */
|
||||
jtag_add_sleep(3000000);
|
||||
|
||||
jtag_add_runtest(2030, TAP_RTI);
|
||||
jtag_execute_queue();
|
||||
|
||||
/* set Hold reset, Halt mode and Trap Reset */
|
||||
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
|
||||
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
|
||||
xscale_write_dcsr(target, 1, 0);
|
||||
jtag_add_runtest(100, TAP_RTI);
|
||||
jtag_execute_queue();
|
||||
|
||||
/* release SRST */
|
||||
jtag_add_reset(0, 0);
|
||||
/* wait 150ms; 100ms were not enough */
|
||||
jtag_add_sleep(150000);
|
||||
|
||||
jtag_add_runtest(2030, TAP_RTI);
|
||||
jtag_execute_queue();
|
||||
|
||||
xscale_write_dcsr(target, 1, 0);
|
||||
jtag_execute_queue();
|
||||
|
||||
/* TODO: load debug handler */
|
||||
if (stat("target/xscale/debug_handler.bin", &binary_stat) == -1)
|
||||
if (fileio_open(&debug_handler, "target/xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
|
||||
{
|
||||
ERROR("couldn't stat() target/xscale/debug_handler.bin: %s", strerror(errno));
|
||||
ERROR("file open error: %s", debug_handler.error_str);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
if (!(binary = fopen("target/xscale/debug_handler.bin", "r")))
|
||||
{
|
||||
ERROR("couldn't open target/xscale/debug_handler.bin: %s", strerror(errno));
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
if ((binary_size = binary_stat.st_size) % 4)
|
||||
|
||||
if ((binary_size = debug_handler.size) % 4)
|
||||
{
|
||||
ERROR("debug_handler.bin: size not a multiple of 4");
|
||||
exit(-1);
|
||||
|
|
@ -1623,41 +1617,51 @@ int xscale_deassert_reset(target_t *target)
|
|||
address = xscale->handler_address;
|
||||
while (binary_size > 0)
|
||||
{
|
||||
buf_cnt = fread(buffer, 4, 8, binary);
|
||||
u32 cache_line[8];
|
||||
u8 buffer[32];
|
||||
|
||||
for (i = 0; i < buf_cnt; i++)
|
||||
if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
|
||||
{
|
||||
/* convert LE buffer to host-endian u32 */
|
||||
buffer[i] = buf_get_u32((u8*)(&buffer[i]), 0, 32);
|
||||
ERROR("reading debug handler failed: %s", debug_handler.error_str);
|
||||
}
|
||||
|
||||
if (buf_cnt < 8)
|
||||
for (i = 0; i < buf_cnt; i += 4)
|
||||
{
|
||||
for (; buf_cnt < 8; buf_cnt++)
|
||||
{
|
||||
buffer[buf_cnt] = 0xe1a08008;
|
||||
}
|
||||
/* convert LE buffer to host-endian u32 */
|
||||
cache_line[i / 4] = le_to_h_u32(&buffer[i]);
|
||||
}
|
||||
|
||||
for (; buf_cnt < 32; buf_cnt += 4)
|
||||
{
|
||||
cache_line[buf_cnt / 4] = 0xe1a08008;
|
||||
}
|
||||
|
||||
/* only load addresses other than the reset vectors */
|
||||
if ((address % 0x400) != 0x0)
|
||||
{
|
||||
xscale_load_ic(target, 1, address, buffer);
|
||||
xscale_load_ic(target, 1, address, cache_line);
|
||||
}
|
||||
|
||||
address += buf_cnt * 4;
|
||||
binary_size -= buf_cnt * 4;
|
||||
address += buf_cnt;
|
||||
binary_size -= buf_cnt;
|
||||
};
|
||||
|
||||
xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
|
||||
xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
|
||||
|
||||
jtag_add_runtest(30, TAP_RTI);
|
||||
|
||||
jtag_add_sleep(100000);
|
||||
|
||||
/* let the target run (should enter debug handler) */
|
||||
xscale_write_dcsr(target, 0, 0);
|
||||
/* set Hold reset, Halt mode and Trap Reset */
|
||||
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
|
||||
buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
|
||||
xscale_write_dcsr(target, 1, 0);
|
||||
|
||||
/* clear Hold reset to let the target run (should enter debug handler) */
|
||||
xscale_write_dcsr(target, 0, 1);
|
||||
target->state = TARGET_RUNNING;
|
||||
|
||||
|
||||
if ((target->reset_mode != RESET_HALT) && (target->reset_mode != RESET_INIT))
|
||||
{
|
||||
jtag_add_sleep(10000);
|
||||
|
|
@ -1666,8 +1670,8 @@ int xscale_deassert_reset(target_t *target)
|
|||
xscale_debug_entry(target);
|
||||
target->state = TARGET_HALTED;
|
||||
|
||||
/* the PC is now at 0x0 */
|
||||
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
|
||||
/* resume the target */
|
||||
xscale_resume(target, 1, 0x0, 1, 0);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -1687,7 +1691,9 @@ int xscale_soft_reset_halt(struct target_s *target)
|
|||
|
||||
int xscale_prepare_reset_halt(struct target_s *target)
|
||||
{
|
||||
/* nothing to be done for reset_halt on XScale targets */
|
||||
/* nothing to be done for reset_halt on XScale targets
|
||||
* we always halt after a reset to upload the debug handler
|
||||
*/
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -2584,6 +2590,10 @@ int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *targe
|
|||
ERROR("Reset target to enable debug");
|
||||
}
|
||||
|
||||
/* assert TRST once during startup */
|
||||
jtag_add_reset(1, 0);
|
||||
jtag_add_reset(0, 0);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue