The AP number value is restricted in 8 bits unsigned by ADI-v5
specification. Nevertheless, an "invalid" value is used by
target cortex-m to force an automatic detection of the AP.
Replace magic numbers by using new macros for AP max number and
for the value of AP invalid.
Check the value passed through -ap-num flag during configuration.
Change-Id: Ic19a367db0ab11c0ebd070750eca0647d25279a5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4668
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The cortex_m maskisr user-facing setting is not changed across a target
reset. However, the in-core C_MASKINTS bit was always cleared as part of
reset processing, meaning that a cortex_m maskisr on setting would not
be respected after a reset. Set C_MASKINTS based on the user-facing
setting value rather than always clearing it after reset.
Change-Id: I5aa5b9dfde04a0fb9c6816fa55b5ef1faf39f8de
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4605
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The code sets C_MASKINTS if that bit is not already set (correctly). Fix
the comment to agree.
Change-Id: If4543e2660a9fa2cdabb2d2698427a6c8d9a274c
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4620
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The vec_ids variable is not referenced anywhere other than the vector
catch command handler. Make it local to that function.
Change-Id: Ie5865e8f78698c19a09f0b9d58269ced1c9db440
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4606
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
If the "Flash Patch and Breakpoint" unit is rev.1 then it can only
accept breakpoint addresses below 0x1FFFFFFF.
Detailed info in "ARM v7-M Architecture Reference Manual", DDI0403E
at chapter "C1.11 Flash Patch and Breakpoint unit".
Print a message and return error if the address of hardware
breakpoint cannot be handled by the breakpoint unit.
Change-Id: I95c92b1f058f0dfc568bf03015f99e439b27c59b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4535
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
Change-Id: I1f3fddd89597333fc1bb9535c0cd76ca3e008324
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4503
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Cortex-M target used 'auto_bp_type' mode. The requested type
of breakpoint was ignored and hard (FPB) breakpoints were set in
'code memory area' 0x00000000-0x1fffffff, soft breakpoints were set above
0x20000000.
The code memory area of Cortex-M does not mean the memory is flash and
vice versa. External flash (parallel or QSPI) is usually mapped above
code memory area. Cortex-M7 ITCM RAM is mapped at 0. Kinetis
has a RAM block under 0x20000000 boundary.
Remove 'auto_bp_type' mode, set breakpoints to requested type.
Change 'cortex_m maskisr auto' handling to use a hard temporary
breakpoint everywhere: it can also workaround not working soft breakpoints
on Cortex-M7 with ICache enabled.
Change-Id: I7a9f9464c5e10bfd7f17cba1037ed07a064fa2e8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4429
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Avoid ever overflowing the DWT_COMPARATOR array by allocating space for
16 comparators (the field is masked by 0xf).
On a stm32f767zi chip (on a nucleo-767zi board) I've been seeing crashes
with address sanitizer enabled due to its (apparent) 10 present
comparators. This appears to be due to
https://sourceforge.net/p/openocd/tickets/178/.
In non-address sanitizer builds, this would likely cause some random
memory to be written to in some cases. (see above bug for observations).
Change-Id: I2b7d599eb326236dbc93f74b350c442c9a502c4b
Signed-off-by: Cody P Schafer <openocd@codyps.com>
Reviewed-on: http://openocd.zylin.com/4458
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
- add 'dap create' command to create dap instances
- move all dap subcmmand into the dap instance commands
- keep 'dap info' for convenience
- change all armv7 and armv8 targets to take a dap
instance instead of a jtag chain position
- restructure tap/dap/target relations, jtag tap no
longer references the dap, daps are now independently
created and initialized.
- clean up swd connect
- re-initialize DAP also on JTAG errors (e.g. after reset,
power cycle)
- update documentation
- update target files
Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4468
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Some of these changes actually fix broken comparisons which could
occasionally fail. Others just clean up the code and make it more clear.
Change-Id: I6c398bdc45fa0d2716f48a74822457d1351f81a5
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4380
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Leverages the existing work that added profiling via DWT_PCSR.
hla_target doesn't have direct access to the mem_ap for doing a bulk
repeated read, but simply reading the DWT_PCSR register repeatedly is
still ~2 order of magnitude faster than halt/resume.
Change-Id: Ibe451aa95143694398370fdad6939cfb6191d56f
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-on: http://openocd.zylin.com/4220
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Use DWT_PCSR if present (reads nonzero); otherwise do halt-and-sample pc.
Signed-off-by: Simon Schubert <2@0x2c.org>
Change-Id: Id2dc4665e5008cc497a2e6e6493522d038d5af42
Reviewed-on: http://openocd.zylin.com/4211
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The dhcsr_save variable was used to save the value of
cortex_m->dcb_dhcsr so it could be restored later. However, all writes
in between the save and the restore use mem_ap_write_atomic_u32, not
cortex_m_write_debug_halt_mask, which means cortex_m->dcb_dhcsr isn’t
changed anyway. Delete the unnecessary local.
Change-Id: I064a3134e21398e1ecfc9f1fa7efd7b020b52341
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4240
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
In cortex_m_assert_reset, in two locations, DHCSR is written directly
using mem_ap_write_u32. This means that the cached version,
target_to_cm(target)->dcb_dhcsr, is not updated when these writes are
performed, so subsequent writes to DHCSR that use
cortex_m_write_debug_halt_mask will change those bits back to their old
values which, unless modified in that particular invocation, come from
the cache. This causes an actual, observable bug on an STM32F7 in which
running “reset run” immediately after “program” can in some cases result
in execution proceeding with C_MASKINTS set (it is cleared on line 1021
but is then set immediately afterward in cortex_m_clear_halt), causing
failure of the application. Replace these mem_ap_write_u32 calls with
cortex_m_write_debug_halt_mask calls to do the same jobs.
Change-Id: Id35ca7f6057c2df2ba9cd67c53a73b50816d0b71
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4239
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Define a target_addr_t type to support 32-bit and 64-bit addresses at
the same time. Also define matching TARGET_PRI*ADDR format macros as
well as a convenient TARGET_ADDR_FMT.
In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000)
be least invasive by leaving the formatting unchanged apart from the
type;
for generic code adopt TARGET_ADDR_FMT as unified address format.
Don't silently change gdb formatting here, leave that to later.
Add COMMAND_PARSE_ADDRESS() macro to abstract the address type.
Implement it using its own parse_target_addr() function, in the hopes
of catching pointer type mismatches better.
Add '--disable-target64' configure option to revert to previous 32-bit
target address behavior.
Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5
Signed-off-by: Dongxue Zhang <elta.era@gmail.com>
Signed-off-by: David Ung <david.ung.42@gmail.com>
[AF: Default to enabling (Paul Fertser), rename macros, simplify]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This patch adds a Cortex-M private configuration option
that allows setting the acess point during target
creation. This circumvents situations in hybrid systems
when the correct access point can not be automatically
detected.
Change-Id: If313a5250e6e66509bb9080f3498feab7781dced
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3639
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This patch adds support for bridging semihosting to GDB's File-I/O
remote protocol extension. For the most part operations match up 1:1,
however some require a working area to complete successfully, namely
operations that devolve to read, stat, and gettimeofday.
A new command was added to enable support for fileio named `arm
semihosting_fileio`, which ensures that the default behavior remains
intact for those that prefer it.
Finally, redundant logging was removed from the target_arch_state
function; this permits ARM targets to quiesce log output when polling
for a fileio reply. This prevents filling the logs with halt/resume
messages when using semihosting fileio.
Change-Id: Ifbb864fc2373336a501cc0332675b887b552e1ee
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/3566
Tested-by: jenkins
Reviewed-by: Steven Stallion <sstallion@gmail.com>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
On multi-core systems, with some cores in power-down state, examination
will fail for these cores. Make sure assert- and deassert_reset functions
don't crash due to uninitialized variables.
Change-Id: I472f8d19af2cd3c770c05f3e57a31b35a863b687
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3552
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Cortex-M7 has autoincrement range only 1024 bytes,
surprisingly smaller than M3, M4.
Change-Id: I35ff1f0e093aac4af79f98eb3b8058d4295942d1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/3737
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
- FPU detection and FPU register support added for Cortex-M7.
There is no apparent difference between FPv4 and FPv5_SP but ...
- Autoincrement range for MEM-AP added for Cortex-M7
This patch together with #3526 replaces #3123 except for stm32f7x.cfg.
Change-Id: I5ed5392e3835674160563ff37d67622a7bf2c877
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/3531
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Also make GPL notices consistent according to:
https://www.gnu.org/licenses/gpl-howto.html
Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/3488
Tested-by: jenkins
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn
or CortexXn. Further it's Cortex-M0+, not M0plus.
Cf. http://www.arm.com/products/processors/index.php
Consistently write it the official way, so that it stops propagating.
Originally spotted in the documentation, it mainly affects code comments
but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output.
Found via:
git grep -i "Cortex "
git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu"
git grep -i "CortexM"
Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-on: http://openocd.zylin.com/3483
Tested-by: jenkins
Reviewed-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Before this change jim_target_reset() checked examined state of a target
and failed without calling .assert_reset in particular target layer
(and without comprehensible warning to user).
Cortex-M target (which refuses access to DP under active SRST):
If connection is lost then reset process fails before asserting SRST
and connection with MCU is not restored.
This resulted in:
1) A lot of Cortex-M MCUs required use of reset button or cycling power
after firmware blocked SWD access somehow (sleep, misconfigured clock etc).
If firmware blocks SWD access early during initialization, a MCU could
become completely inaccessible by SWD.
2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive
to SWD, reset command does not work even if it could help to restore communication.
Hopefully this scenario is not possible under full JTAG.
jim_target_reset() in target.c now does not check examined state
and delegates this task to a particular target. All targets have been checked
and xx_assert_reset() (or xx_deassert_reset()) procedures were changed
to check examined state if needed. Targets except arm11, cortex_a and cortex_m
just fail if target is not examined although it may be possible to use
at least hw reset. Left as TODO for developers familiar with these targets.
cortex_m_assert_reset(): memory access errors are stored
instead of immediate returning them to a higher level.
Errors from less important reads/writes are ignored.
Requested reset always leads to a configured action.
arm11_assert_reset() just asserts hw reset in case of not examined target.
cortex_a_assert_reset() works as usual in case of not examined target.
Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2606
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
The HLA target shares an examine handler with cortex_m but since it
lacks direct access to DAP, some operations need to be omitted.
Change-Id: Ifdd9d3da4a3a3c2e1c9721284b21d041b3ccaa7a
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3183
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
It's currently set during target creation but the AP that will be used
for the target is not even known.
Change-Id: I4502e7eb1fa8d90f746445b8cf8a4c21cb7d519e
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3155
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
All mem_ap_* functions now make sure the SELECT register is updated with
the AP number that it's operating on. This shouldn't have to be handled
explicitly.
Change-Id: Ib193d8930fabb6a25715064355f98258c9580b5d
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3153
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This function does two separate things, powering up the DP and setting
up a MEM-AP. But the DP needs to be powered before even searching for a
MEM-AP to initialize and targets may have multiple MEM-APs that need
initializing.
Split the function into dap_dp_init() and mem_ap_init() and change all
call sites to use the appropriate one.
Change-Id: I92f55e09754a93f3f01dd8e5aa1ffdf60c856126
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3151
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Change the debug_ap and memory_ap fields of the cortex_a target and
the debug_ap field of the cortex_m target to be pointers to the
struct adiv5_ap instead of AP numbers in some known DAP.
This reduces the dependency on the DAP struct in the targets and
enables MEM-AP accesses to take the relevant AP as parameter.
Change-Id: I39d7b134d78000564b7eec5bff464adf0ef89147
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3147
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This required fixing the AP ID parsing in dap_find_ap() to
match IHI0031C. The AXI type was added too.
Change-Id: I44577a7848df37586e650dce0fb57ac26f5f858c
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3146
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be
able to pass a pointer to it to one common JTAG function which anyway
only uses the TAP field.
Refactor the function to take a TAP directly, remove the legacy struct
from cortex instances and store the TAP pointer only in the DAP.
Cortex-M makes a call to arm_jtag_setup_connection() with the struct
but the function does nothing useful for a Cortex-M target so remove
the call.
Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/3142
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Separate out the values from adiv5_dap that are associated with a specific AP into a new struct, so we can properly support multiple APs. Remove the DAP struct from the armv7* structs, because we can have multiple CPUs per DAP, and we shouldn't have multiple DAP structs. Tidy up a few places where ap_current is used incorrectly.
Change-Id: I0c6ef4b49cc86b140366347aaf9b76c07cbab0a8
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Reviewed-on: http://openocd.zylin.com/2984
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Prepare to support multiple cortex-m cores on one DAP. Uses mem_ap_sel_*
functions and removes mem_ap_* functions. Adds a new debug_ap
parameter to the cortex_m (currently set to zero as in existing code).
Change-Id: I6926029d1e7bf44a42d453d1aff349bda824ba72
Signed-off-by: Patrick Stewart <patstew@gmail.com>
Reviewed-on: http://openocd.zylin.com/2983
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
A segmentation fault in cortex_m_endreset_event() is sometimes raised
with very broken target like Kinetis Kx with erased flash and active WDOG.
Debugging revealed that cortex_m->dwt_num_comp is 4 and
dwt_list is NULL at cortex_m:290
Change-Id: I229c59d6da13d816df513d1dbb19968e4b5951e2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/2989
Reviewed-by: Thomas Schmid <thomas@rfranging.com>
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Some targets need arbitrary amount of time (usually not too long)
after reset (both sysresetreq and srst) to do initialisation, and
SWD/JTAG is not available during that. According to PSoC4 docs, the
debugger should try connecting until it succeeds.
Also ahbap_debugport_init might be necessary to perform after using
hardware srst too, so add it there (except for the targets that
support srst_nogate since they are very unlikely to need it).
Change-Id: I3598d5ff7b8e0bf3a5566a57dec4b0b2b243d297
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2601
Tested-by: jenkins
This brings SWD reconnection procedure in line with the ARM
documentation and changes cortex_m reset procedure to make use of it.
The motivation behind this patch is to make SAM4L "reset" and "reset
halt" properly without SRST. The complication here is that EDBG issues
an additional read of DP_RDBUFF automatically right after writing
SYSRESETREQ, that leads to a FAULT which needs to be dealt with
properly. With this patch the very first ahbap_debugport_init DAP
access will make SWD layer properly reinitialise the link before
continuing.
Runtime tested with mbed CMIS-DAP + KL25 only.
Change-Id: Ic506f9db30931dfa60860036b83f73b897975909
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2596
Tested-by: jenkins
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This provides support for various trace-related subsystems in a
generic and expandable way.
Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2538
Tested-by: jenkins
This should facilitate dynamic target creation and removal.
Currently it helps with getting 0 bytes lost report from Valgrind on
exit (after talking to a nucleo board). However, 1,223,886 bytes in
5,268 blocks are still reachable which means the app holds pointers to
that data on exit. The majority comes from the jtag command queue,
there're also many blocks from TCL command registration.
Change-Id: I7523234bb90fffd26f7d29cdd7648ddd221d46ab
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2544
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
This bug was exposed by Valgrind.
Change-Id: If50878664d928c0a44e309ca1452089c1ac71466
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2542
Tested-by: jenkins
Reviewed-by: Stian Skjelstad <stian@nixia.no>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This is runtime and valgrind tested with l0, l1 and f3 hla boards.
Change-Id: I49b0b042253d5f3bf216997f0203583db319fe23
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2516
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This patch adds the fpv4-sp-d16 registers to the armv7m register set.
The work is inspired by Mathias K but takes a different approach:
instead of having both double and single presicion registers in the
cache this patch works only with the doubles and counts on GDB to
split the data in halves whenever needed.
Tested with HLA only (on an STM32F334 disco board).
Currently this patch makes all ARMv7-M targets report an FPU-enabled
target description to GDB. It shouldn't harm if the user is not trying
to access non-existing FPU. However, the plan is to make this depend
on actual FPU presence later.
Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a
Signed-off-by: Mathias K <kesmtp@freenet.de>
[fercerpav@gmail.com: rework to fit target description framework]
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/514
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Convert the DWT register store to use a byte array and fix the byte order
bug uncovered by that. Also fix an incorrect access of the PC value.
Change-Id: Idb5acab71bdf5a96895c358324b05c335e4d32ca
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: http://openocd.zylin.com/2476
Tested-by: jenkins
Reviewed-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Remove double readout of DCB_DHCSR in target poll. The return value
of the endreset event is handled and not ignored in target poll.
Change-Id: I8fe026418dadcf0b0dcbb09acee871ad950937a2
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/1181
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
SAM4L requires additional steps to be taken right after SYSRESETREQ is
issued in order to function robustly:
- CMSIS-DAP DAP driver needs to explicitly check for sticky bit
errors since it is possible for adapter to perform successful
write opration, report no errors and then, under the hood, do
some other things that will result in sticky bit being set.
- Debugger needs to wait for security system to finish
intialization and assert CDBGPWRUPACK before proceeding
This change is related to commit http://openocd.zylin.com/#/c/1995/
Change-Id: I741c95a809bfd60d930cec9482239e4796a62326
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2088
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com>
