# SPDX-License-Identifier: GPL-2.0-or-later
# Cadence virtual debug interface
# Arm Cortex A53x2 through JTAG

source [find interface/vdebug.cfg]

set _CORES 2
set _CHIPNAME a53
set _MEMSTART 0x00000000
set _MEMSIZE 0x1000000
set _CPUTAPID 0x5ba00477

# vdebug select transport
transport select jtag

# JTAG reset config, frequency and reset delay
reset_config trst_and_srst
adapter speed 50000
adapter srst delay 5

# BFM hierarchical path and input clk period
vdebug bfm_path tbench.u_vd_jtag_bfm 10ns

# DMA Memories to access backdoor (up to 4)
vdebug mem_path tbench.u_memory.mem_array $_MEMSTART $_MEMSIZE

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

jtag arp_init-reset

source [find target/vd_aarch64.cfg]