/***************************************************************************
* Copyright (C) 2016 - 2018 by Andreas Bolsch *
* andreas.bolsch@mni.thm.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see . *
***************************************************************************/
#ifndef OPENOCD_FLASH_NOR_STMQSPI_H
#define OPENOCD_FLASH_NOR_STMQSPI_H
#include "spi.h"
/* QSPI register offsets */
#define QSPI_CR (0x00) /* Control register */
#define QSPI_DCR (0x04) /* Device configuration register */
#define QSPI_SR (0x08) /* Status register */
#define QSPI_FCR (0x0C) /* Flag clear register */
#define QSPI_DLR (0x10) /* Data length register */
#define QSPI_CCR (0x14) /* Communication configuration register */
#define QSPI_AR (0x18) /* Address register */
#define QSPI_ABR (0x1C) /* Alternate bytes register */
#define QSPI_DR (0x20) /* Data register */
/* common bits in QSPI_CR and OCTOSPI_CR */
#define SPI_FSEL_FLASH 7 /* Select flash 2 */
#define SPI_DUAL_FLASH 6 /* Dual flash mode */
#define SPI_ABORT 1 /* Abort bit */
/* common bits in QSPI_DCR and OCTOSPI_DCR1 */
#define SPI_FSIZE_POS 16 /* bit position of FSIZE */
#define SPI_FSIZE_LEN 5 /* width of FSIZE field */
/* common bits in QSPI_SR/FCR and OCTOSPI_SR/FCR */
#define SPI_BUSY 5 /* Busy flag */
#define SPI_FTF 2 /* FIFO threshold flag */
#define SPI_TCF 1 /* Transfer complete flag */
/* fields in QSPI_CCR */
#define QSPI_DDRM 31 /* position of DDRM bit */
#define SPI_DMODE_POS 24 /* bit position of DMODE */
#define QSPI_DCYC_POS 18 /* bit position of DCYC */
#define QSPI_DCYC_LEN 5 /* width of DCYC field */
#define QSPI_DCYC_MASK (((1U<octo)
#define SPI_CR (IS_OCTOSPI ? OCTOSPI_CR : QSPI_CR)
#define SPI_DCR (IS_OCTOSPI ? OCTOSPI_DCR1 : QSPI_DCR)
#define SPI_SR (IS_OCTOSPI ? OCTOSPI_SR : QSPI_SR)
#define SPI_FCR (IS_OCTOSPI ? OCTOSPI_FCR : QSPI_FCR)
#define SPI_DLR (IS_OCTOSPI ? OCTOSPI_DLR : QSPI_DLR)
#define SPI_AR (IS_OCTOSPI ? OCTOSPI_AR : QSPI_AR)
#define SPI_DR (IS_OCTOSPI ? OCTOSPI_DR : QSPI_DR)
#define SPI_CCR (IS_OCTOSPI ? OCTOSPI_CCR : QSPI_CCR)
#endif /* OPENOCD_FLASH_NOR_STMQSPI_H */