225 lines
5.0 KiB
C
225 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2013 by Andes Technology *
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* Hsiangkai Wang <hkwang@andestech.com> *
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***************************************************************************/
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#ifndef OPENOCD_JTAG_AICE_AICE_PORT_H
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#define OPENOCD_JTAG_AICE_AICE_PORT_H
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#include <target/nds32_edm.h>
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#define AICE_MAX_NUM_CORE (0x10)
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#define ERROR_AICE_DISCONNECT (-200)
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#define ERROR_AICE_TIMEOUT (-201)
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enum aice_target_state_s {
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AICE_DISCONNECT = 0,
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AICE_TARGET_DETACH,
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AICE_TARGET_UNKNOWN,
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AICE_TARGET_RUNNING,
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AICE_TARGET_HALTED,
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AICE_TARGET_RESET,
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AICE_TARGET_DEBUG_RUNNING,
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};
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enum aice_srst_type_s {
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AICE_SRST = 0x1,
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AICE_RESET_HOLD = 0x8,
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};
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enum aice_target_endian {
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AICE_LITTLE_ENDIAN = 0,
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AICE_BIG_ENDIAN,
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};
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enum aice_api_s {
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AICE_OPEN = 0x0,
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AICE_CLOSE,
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AICE_RESET,
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AICE_IDCODE,
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AICE_SET_JTAG_CLOCK,
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AICE_ASSERT_SRST,
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AICE_RUN,
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AICE_HALT,
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AICE_STEP,
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AICE_READ_REG,
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AICE_WRITE_REG,
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AICE_READ_REG_64,
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AICE_WRITE_REG_64,
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AICE_READ_MEM_UNIT,
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AICE_WRITE_MEM_UNIT,
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AICE_READ_MEM_BULK,
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AICE_WRITE_MEM_BULK,
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AICE_READ_DEBUG_REG,
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AICE_WRITE_DEBUG_REG,
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AICE_STATE,
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AICE_MEMORY_ACCESS,
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AICE_MEMORY_MODE,
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AICE_READ_TLB,
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AICE_CACHE_CTL,
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AICE_SET_RETRY_TIMES,
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AICE_PROGRAM_EDM,
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AICE_SET_COMMAND_MODE,
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AICE_EXECUTE,
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AICE_SET_CUSTOM_SRST_SCRIPT,
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AICE_SET_CUSTOM_TRST_SCRIPT,
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AICE_SET_CUSTOM_RESTART_SCRIPT,
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AICE_SET_COUNT_TO_CHECK_DBGER,
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AICE_SET_DATA_ENDIAN,
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};
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enum aice_error_s {
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AICE_OK,
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AICE_ACK,
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AICE_ERROR,
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};
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enum aice_cache_ctl_type {
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AICE_CACHE_CTL_L1D_INVALALL = 0,
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AICE_CACHE_CTL_L1D_VA_INVAL,
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AICE_CACHE_CTL_L1D_WBALL,
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AICE_CACHE_CTL_L1D_VA_WB,
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AICE_CACHE_CTL_L1I_INVALALL,
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AICE_CACHE_CTL_L1I_VA_INVAL,
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};
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enum aice_command_mode {
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AICE_COMMAND_MODE_NORMAL,
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AICE_COMMAND_MODE_PACK,
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AICE_COMMAND_MODE_BATCH,
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};
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struct aice_port_param_s {
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/** */
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const char *device_desc;
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/** */
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uint16_t vid;
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/** */
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uint16_t pid;
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/** */
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char *adapter_name;
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};
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struct aice_port_s {
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/** */
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uint32_t coreid;
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/** */
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const struct aice_port *port;
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};
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/** */
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extern struct aice_port_api_s aice_usb_layout_api;
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/** */
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struct aice_port_api_s {
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/** */
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int (*open)(struct aice_port_param_s *param);
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/** */
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int (*close)(void);
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/** */
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int (*reset)(void);
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/** */
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int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
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/** */
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int (*set_jtag_clock)(uint32_t a_clock);
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/** */
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int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
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/** */
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int (*run)(uint32_t coreid);
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/** */
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int (*halt)(uint32_t coreid);
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/** */
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int (*step)(uint32_t coreid);
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/** */
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int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
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/** */
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int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
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/** */
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int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
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/** */
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int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
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/** */
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int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
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uint32_t count, uint8_t *buffer);
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/** */
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int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
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uint32_t count, const uint8_t *buffer);
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/** */
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int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
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uint8_t *buffer);
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/** */
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int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
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const uint8_t *buffer);
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/** */
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int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
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/** */
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int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
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/** */
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int (*state)(uint32_t coreid, enum aice_target_state_s *state);
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/** */
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int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
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/** */
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int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
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/** */
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int (*read_tlb)(uint32_t coreid, target_addr_t virtual_address, target_addr_t *physical_address);
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/** */
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int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
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/** */
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int (*set_retry_times)(uint32_t a_retry_times);
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/** */
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int (*program_edm)(uint32_t coreid, char *command_sequence);
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/** */
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int (*set_command_mode)(enum aice_command_mode command_mode);
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/** */
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int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
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/** */
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int (*set_custom_srst_script)(const char *script);
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/** */
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int (*set_custom_trst_script)(const char *script);
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/** */
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int (*set_custom_restart_script)(const char *script);
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/** */
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int (*set_count_to_check_dbger)(uint32_t count_to_check);
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/** */
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int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
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/** */
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int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
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uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
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};
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#define AICE_PORT_UNKNOWN 0
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#define AICE_PORT_AICE_USB 1
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#define AICE_PORT_AICE_PIPE 2
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/** */
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struct aice_port {
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/** */
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const char *name;
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/** */
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int type;
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/** */
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struct aice_port_api_s *const api;
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};
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/** */
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const struct aice_port *aice_port_get_list(void);
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#endif /* OPENOCD_JTAG_AICE_AICE_PORT_H */
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