85 lines
3.0 KiB
C
85 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2015 by Daniel Krebs *
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* Daniel Krebs - github@daniel-krebs.net *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "rtos.h"
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#include "target/armv7m.h"
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#include "rtos_standard_stackings.h"
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/* This works for the M0 and M34 stackings as xPSR is in a fixed
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* location
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*/
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static target_addr_t rtos_riot_cortex_m_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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target_addr_t stack_ptr)
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{
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const int XPSR_OFFSET = 0x40;
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return rtos_cortex_m_stack_align(target, stack_data, stacking,
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stack_ptr, XPSR_OFFSET);
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}
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/* see thread_arch.c */
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static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ ARMV7M_R0, 0x24, 32 }, /* r0 */
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{ ARMV7M_R1, 0x28, 32 }, /* r1 */
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{ ARMV7M_R2, 0x2c, 32 }, /* r2 */
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{ ARMV7M_R3, 0x30, 32 }, /* r3 */
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{ ARMV7M_R4, 0x14, 32 }, /* r4 */
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{ ARMV7M_R5, 0x18, 32 }, /* r5 */
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{ ARMV7M_R6, 0x1c, 32 }, /* r6 */
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{ ARMV7M_R7, 0x20, 32 }, /* r7 */
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{ ARMV7M_R8, 0x04, 32 }, /* r8 */
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{ ARMV7M_R9, 0x08, 32 }, /* r9 */
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{ ARMV7M_R10, 0x0c, 32 }, /* r10 */
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{ ARMV7M_R11, 0x10, 32 }, /* r11 */
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{ ARMV7M_R12, 0x34, 32 }, /* r12 */
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{ ARMV7M_R13, -2, 32 }, /* sp */
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{ ARMV7M_R14, 0x38, 32 }, /* lr */
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{ ARMV7M_PC, 0x3c, 32 }, /* pc */
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{ ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
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};
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const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
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.stack_registers_size = 0x44,
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.stack_growth_direction = -1,
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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.calculate_process_stack = rtos_riot_cortex_m_stack_align,
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.register_offsets = rtos_riot_cortex_m0_stack_offsets
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};
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/* see thread_arch.c */
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static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ ARMV7M_R0, 0x24, 32 }, /* r0 */
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{ ARMV7M_R1, 0x28, 32 }, /* r1 */
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{ ARMV7M_R2, 0x2c, 32 }, /* r2 */
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{ ARMV7M_R3, 0x30, 32 }, /* r3 */
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{ ARMV7M_R4, 0x04, 32 }, /* r4 */
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{ ARMV7M_R5, 0x08, 32 }, /* r5 */
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{ ARMV7M_R6, 0x0c, 32 }, /* r6 */
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{ ARMV7M_R7, 0x10, 32 }, /* r7 */
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{ ARMV7M_R8, 0x14, 32 }, /* r8 */
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{ ARMV7M_R9, 0x18, 32 }, /* r9 */
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{ ARMV7M_R10, 0x1c, 32 }, /* r10 */
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{ ARMV7M_R11, 0x20, 32 }, /* r11 */
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{ ARMV7M_R12, 0x34, 32 }, /* r12 */
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{ ARMV7M_R13, -2, 32 }, /* sp */
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{ ARMV7M_R14, 0x38, 32 }, /* lr */
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{ ARMV7M_PC, 0x3c, 32 }, /* pc */
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{ ARMV7M_xPSR, 0x40, 32 }, /* xPSR */
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};
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const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
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.stack_registers_size = 0x44,
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.stack_growth_direction = -1,
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.num_output_registers = ARMV7M_NUM_CORE_REGS,
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.calculate_process_stack = rtos_riot_cortex_m_stack_align,
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.register_offsets = rtos_riot_cortex_m34_stack_offsets
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};
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