104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2008 digenius technology GmbH. *
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* Michael Bruck *
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* *
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* Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARM11_H
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#define OPENOCD_TARGET_ARM11_H
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#include "arm.h"
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#include "arm_dpm.h"
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#define ARM11_TAP_DEFAULT TAP_INVALID
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#define CHECK_RETVAL(action) \
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do { \
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int __retval = (action); \
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if (__retval != ERROR_OK) { \
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LOG_DEBUG("error while calling \"%s\"", \
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# action); \
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return __retval; \
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} \
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} while (0)
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/* bits from ARMv7 DIDR */
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enum arm11_debug_version {
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ARM11_DEBUG_V6 = 0x01,
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ARM11_DEBUG_V61 = 0x02,
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ARM11_DEBUG_V7 = 0x03,
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ARM11_DEBUG_V7_CP14 = 0x04,
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};
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struct arm11_common {
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struct arm arm;
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/** Debug module state. */
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struct arm_dpm dpm;
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struct arm11_sc7_action *bpwp_actions;
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unsigned bpwp_n;
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size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
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size_t free_brps; /**< Number of breakpoints allocated */
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uint32_t dscr; /**< Last retrieved DSCR value. */
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uint32_t saved_rdtr;
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uint32_t saved_wdtr;
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bool is_rdtr_saved;
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bool is_wdtr_saved;
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bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt **/
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/* Per-core configurable options.
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* NOTE that several of these boolean options should not exist
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* once the relevant code is known to work correctly.
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*/
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bool memwrite_burst;
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bool memwrite_error_fatal;
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bool step_irq_enable;
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bool hardware_step;
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/** Configured Vector Catch Register settings. */
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uint32_t vcr;
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struct arm_jtag jtag_info;
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};
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static inline struct arm11_common *target_to_arm11(struct target *target)
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{
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return container_of(target->arch_info, struct arm11_common, arm);
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}
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/**
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* ARM11 DBGTAP instructions
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*
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* http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
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*/
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enum arm11_instructions {
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ARM11_EXTEST = 0x00,
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ARM11_SCAN_N = 0x02,
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ARM11_RESTART = 0x04,
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ARM11_HALT = 0x08,
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ARM11_INTEST = 0x0C,
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ARM11_ITRSEL = 0x1D,
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ARM11_IDCODE = 0x1E,
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ARM11_BYPASS = 0x1F,
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};
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enum arm11_sc7 {
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ARM11_SC7_NULL = 0,
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ARM11_SC7_VCR = 7,
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ARM11_SC7_PC = 8,
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ARM11_SC7_BVR0 = 64,
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ARM11_SC7_BCR0 = 80,
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ARM11_SC7_WVR0 = 96,
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ARM11_SC7_WCR0 = 112,
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};
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#endif /* OPENOCD_TARGET_ARM11_H */
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