505 lines
14 KiB
C
505 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2009 by Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "arm720t.h"
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#include <helper/time_support.h>
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#include "target_type.h"
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#include "register.h"
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#include "arm_opcodes.h"
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/*
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* ARM720 is an ARM7TDMI-S with MMU and ETM7. For information, see
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* ARM DDI 0229C especially Chapter 9 about debug support.
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*/
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#if 0
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#define _DEBUG_INSTRUCTION_EXECUTION_
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#endif
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static int arm720t_scan_cp15(struct target *target,
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uint32_t out, uint32_t *in, int instruction, int clock_arg)
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{
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int retval;
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struct arm720t_common *arm720t = target_to_arm720(target);
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struct arm_jtag *jtag_info;
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struct scan_field fields[2];
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uint8_t out_buf[4];
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uint8_t instruction_buf = instruction;
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jtag_info = &arm720t->arm7_9_common.jtag_info;
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buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
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retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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fields[0].num_bits = 1;
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fields[0].out_value = &instruction_buf;
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fields[0].in_value = NULL;
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fields[1].num_bits = 32;
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fields[1].out_value = out_buf;
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fields[1].in_value = NULL;
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if (in) {
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fields[1].in_value = (uint8_t *)in;
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jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
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jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
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} else
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jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
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if (clock_arg)
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jtag_add_runtest(0, TAP_DRPAUSE);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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if (in)
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LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
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else
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LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
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#else
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LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
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#endif
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return ERROR_OK;
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}
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static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
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{
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/* fetch CP15 opcode */
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arm720t_scan_cp15(target, opcode, NULL, 1, 1);
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/* "DECODE" stage */
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arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
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/* "EXECUTE" stage (1) */
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arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
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arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
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/* "EXECUTE" stage (2) */
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arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
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/* "EXECUTE" stage (3), CDATA is read */
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arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
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return ERROR_OK;
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}
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static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
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{
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/* fetch CP15 opcode */
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arm720t_scan_cp15(target, opcode, NULL, 1, 1);
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/* "DECODE" stage */
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arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
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/* "EXECUTE" stage (1) */
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arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
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arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
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/* "EXECUTE" stage (2) */
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arm720t_scan_cp15(target, value, NULL, 0, 1);
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arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
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return ERROR_OK;
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}
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static int arm720t_get_ttb(struct target *target, uint32_t *result)
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{
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uint32_t ttb = 0x0;
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int retval;
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retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
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if (retval != ERROR_OK)
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return retval;
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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ttb &= 0xffffc000;
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*result = ttb;
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return ERROR_OK;
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}
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static int arm720t_disable_mmu_caches(struct target *target,
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int mmu, int d_u_cache, int i_cache)
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{
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uint32_t cp15_control;
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int retval;
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/* read cp15 control register */
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retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
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if (retval != ERROR_OK)
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return retval;
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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if (mmu)
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cp15_control &= ~0x1U;
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if (d_u_cache || i_cache)
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cp15_control &= ~0x4U;
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retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
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return retval;
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}
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static int arm720t_enable_mmu_caches(struct target *target,
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int mmu, int d_u_cache, int i_cache)
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{
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uint32_t cp15_control;
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int retval;
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/* read cp15 control register */
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retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
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if (retval != ERROR_OK)
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return retval;
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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if (mmu)
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cp15_control |= 0x1U;
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if (d_u_cache || i_cache)
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cp15_control |= 0x4U;
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retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
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return retval;
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}
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static int arm720t_post_debug_entry(struct target *target)
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{
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struct arm720t_common *arm720t = target_to_arm720(target);
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int retval;
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/* examine cp15 control reg */
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retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
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if (retval != ERROR_OK)
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return retval;
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
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arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
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arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
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arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
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/* save i/d fault status and address register */
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retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
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if (retval != ERROR_OK)
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return retval;
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retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
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if (retval != ERROR_OK)
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return retval;
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retval = jtag_execute_queue();
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return retval;
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}
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static void arm720t_pre_restore_context(struct target *target)
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{
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struct arm720t_common *arm720t = target_to_arm720(target);
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/* restore i/d fault status and address register */
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arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
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arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
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}
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static int arm720t_arch_state(struct target *target)
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{
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struct arm720t_common *arm720t = target_to_arm720(target);
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static const char *state[] = {
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"disabled", "enabled"
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};
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arm_arch_state(target);
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LOG_USER("MMU: %s, Cache: %s",
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state[arm720t->armv4_5_mmu.mmu_enabled],
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state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
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return ERROR_OK;
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}
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static int arm720_mmu(struct target *target, int *enabled)
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{
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("%s: target not halted", __func__);
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return ERROR_TARGET_INVALID;
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}
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*enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
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return ERROR_OK;
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}
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static int arm720_virt2phys(struct target *target,
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target_addr_t virtual, target_addr_t *physical)
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{
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uint32_t cb;
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struct arm720t_common *arm720t = target_to_arm720(target);
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uint32_t ret;
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int retval = armv4_5_mmu_translate_va(target,
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&arm720t->armv4_5_mmu, virtual, &cb, &ret);
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if (retval != ERROR_OK)
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return retval;
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*physical = ret;
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return ERROR_OK;
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}
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static int arm720t_read_memory(struct target *target,
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target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int retval;
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struct arm720t_common *arm720t = target_to_arm720(target);
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/* disable cache, but leave MMU enabled */
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if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
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retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
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if (retval != ERROR_OK)
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return retval;
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}
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retval = arm7_9_read_memory(target, address, size, count, buffer);
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if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
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retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
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if (retval != ERROR_OK)
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return retval;
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}
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return retval;
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}
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static int arm720t_read_phys_memory(struct target *target,
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target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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{
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struct arm720t_common *arm720t = target_to_arm720(target);
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return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
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}
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static int arm720t_write_phys_memory(struct target *target,
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target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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struct arm720t_common *arm720t = target_to_arm720(target);
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return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
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}
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static int arm720t_soft_reset_halt(struct target *target)
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{
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int retval = ERROR_OK;
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struct arm720t_common *arm720t = target_to_arm720(target);
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struct reg *dbg_stat = &arm720t->arm7_9_common
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.eice_cache->reg_list[EICE_DBG_STAT];
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struct arm *arm = &arm720t->arm7_9_common.arm;
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retval = target_halt(target);
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if (retval != ERROR_OK)
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return retval;
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int64_t then = timeval_ms();
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int timeout;
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while (!(timeout = ((timeval_ms()-then) > 1000))) {
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if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
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embeddedice_read_reg(dbg_stat);
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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} else
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break;
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if (debug_level >= 3)
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alive_sleep(100);
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else
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keep_alive();
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}
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if (timeout) {
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LOG_ERROR("Failed to halt CPU after 1 sec");
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return ERROR_TARGET_TIMEOUT;
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}
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target->state = TARGET_HALTED;
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/* SVC, ARM state, IRQ and FIQ disabled */
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uint32_t cpsr;
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cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
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cpsr &= ~0xff;
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cpsr |= 0xd3;
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arm_set_cpsr(arm, cpsr);
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arm->cpsr->dirty = true;
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/* start fetching from 0x0 */
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buf_set_u32(arm->pc->value, 0, 32, 0x0);
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arm->pc->dirty = true;
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arm->pc->valid = true;
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retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
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if (retval != ERROR_OK)
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return retval;
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arm720t->armv4_5_mmu.mmu_enabled = 0;
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arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
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arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
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retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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if (retval != ERROR_OK)
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return retval;
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return ERROR_OK;
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}
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static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
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{
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return arm7tdmi_init_target(cmd_ctx, target);
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}
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static void arm720t_deinit_target(struct target *target)
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{
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arm7tdmi_deinit_target(target);
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}
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/* FIXME remove forward decls */
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static int arm720t_mrc(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t crn, uint32_t crm,
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uint32_t *value);
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static int arm720t_mcr(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t crn, uint32_t crm,
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uint32_t value);
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static int arm720t_init_arch_info(struct target *target,
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struct arm720t_common *arm720t, struct jtag_tap *tap)
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{
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struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
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arm7_9->arm.mrc = arm720t_mrc;
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arm7_9->arm.mcr = arm720t_mcr;
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arm7tdmi_init_arch_info(target, arm7_9, tap);
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arm720t->common_magic = ARM720T_COMMON_MAGIC;
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arm7_9->post_debug_entry = arm720t_post_debug_entry;
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arm7_9->pre_restore_context = arm720t_pre_restore_context;
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arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
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arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
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arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
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arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
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arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
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arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
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arm720t->armv4_5_mmu.has_tiny_pages = 0;
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arm720t->armv4_5_mmu.mmu_enabled = 0;
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return ERROR_OK;
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}
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static int arm720t_target_create(struct target *target, Jim_Interp *interp)
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{
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struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
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arm720t->arm7_9_common.arm.arch = ARM_ARCH_V4;
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return arm720t_init_arch_info(target, arm720t, target->tap);
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}
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static int arm720t_mrc(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t crn, uint32_t crm,
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uint32_t *value)
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{
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if (cpnum != 15) {
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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/* read "to" r0 */
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return arm720t_read_cp15(target,
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ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
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value);
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}
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static int arm720t_mcr(struct target *target, int cpnum,
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uint32_t op1, uint32_t op2,
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uint32_t crn, uint32_t crm,
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uint32_t value)
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{
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if (cpnum != 15) {
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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/* write "from" r0 */
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return arm720t_write_cp15(target,
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ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
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value);
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}
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static const struct command_registration arm720t_command_handlers[] = {
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{
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.chain = arm7_9_command_handlers,
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},
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COMMAND_REGISTRATION_DONE
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};
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/** Holds methods for ARM720 targets. */
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struct target_type arm720t_target = {
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.name = "arm720t",
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.poll = arm7_9_poll,
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.arch_state = arm720t_arch_state,
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.halt = arm7_9_halt,
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.resume = arm7_9_resume,
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.step = arm7_9_step,
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.assert_reset = arm7_9_assert_reset,
|
|
.deassert_reset = arm7_9_deassert_reset,
|
|
.soft_reset_halt = arm720t_soft_reset_halt,
|
|
|
|
.get_gdb_arch = arm_get_gdb_arch,
|
|
.get_gdb_reg_list = arm_get_gdb_reg_list,
|
|
|
|
.read_memory = arm720t_read_memory,
|
|
.write_memory = arm7_9_write_memory_opt,
|
|
.read_phys_memory = arm720t_read_phys_memory,
|
|
.write_phys_memory = arm720t_write_phys_memory,
|
|
.mmu = arm720_mmu,
|
|
.virt2phys = arm720_virt2phys,
|
|
|
|
.checksum_memory = arm_checksum_memory,
|
|
.blank_check_memory = arm_blank_check_memory,
|
|
|
|
.run_algorithm = armv4_5_run_algorithm,
|
|
|
|
.add_breakpoint = arm7_9_add_breakpoint,
|
|
.remove_breakpoint = arm7_9_remove_breakpoint,
|
|
.add_watchpoint = arm7_9_add_watchpoint,
|
|
.remove_watchpoint = arm7_9_remove_watchpoint,
|
|
|
|
.commands = arm720t_command_handlers,
|
|
.target_create = arm720t_target_create,
|
|
.init_target = arm720t_init_target,
|
|
.deinit_target = arm720t_deinit_target,
|
|
.examine = arm7_9_examine,
|
|
.check_reset = arm7_9_check_reset,
|
|
};
|