723 lines
22 KiB
C
723 lines
22 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2007,2008 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "arm7tdmi.h"
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#include "target_type.h"
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#include "register.h"
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#include "arm_opcodes.h"
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#include "arm_semihosting.h"
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/*
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* For information about ARM7TDMI, see ARM DDI 0210C (r4p1)
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* or ARM DDI 0029G (r3). "Debug In Depth", Appendix B,
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* covers JTAG support.
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*/
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#if 0
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#define _DEBUG_INSTRUCTION_EXECUTION_
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#endif
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static int arm7tdmi_examine_debug_reason(struct target *target)
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{
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int retval = ERROR_OK;
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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/* only check the debug reason if we don't know it already */
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if ((target->debug_reason != DBG_REASON_DBGRQ)
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&& (target->debug_reason != DBG_REASON_SINGLESTEP)) {
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struct scan_field fields[2];
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uint8_t databus[4];
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uint8_t breakpoint;
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fields[0].num_bits = 1;
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fields[0].out_value = NULL;
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fields[0].in_value = &breakpoint;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].in_value = databus;
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retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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retval = arm_jtag_set_instr(arm7_9->jtag_info.tap, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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fields[0].in_value = NULL;
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fields[0].out_value = &breakpoint;
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fields[1].in_value = NULL;
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fields[1].out_value = databus;
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jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
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if (breakpoint & 1)
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target->debug_reason = DBG_REASON_WATCHPOINT;
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else
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target->debug_reason = DBG_REASON_BREAKPOINT;
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}
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return ERROR_OK;
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}
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static const int arm7tdmi_num_bits[] = {1, 32};
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static inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_t out, int breakpoint)
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{
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uint8_t bp = breakpoint ? 1 : 0;
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uint8_t out_value[4];
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buf_set_u32(out_value, 0, 32, flip_u32(out, 32));
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struct scan_field fields[2] = {
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{ .num_bits = arm7tdmi_num_bits[0], .out_value = &bp },
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{ .num_bits = arm7tdmi_num_bits[1], .out_value = out_value },
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};
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jtag_add_dr_scan(jtag_info->tap,
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2,
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fields,
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TAP_DRPAUSE);
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jtag_add_runtest(0, TAP_DRPAUSE);
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return ERROR_OK;
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}
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/* put an instruction in the ARM7TDMI pipeline or write the data bus,
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* and optionally read data
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*/
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static inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
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uint32_t out, int breakpoint)
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{
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int retval;
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retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
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}
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/* clock the target, reading the databus */
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static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
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{
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int retval = ERROR_OK;
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struct scan_field fields[2];
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retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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fields[0].num_bits = 1;
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fields[0].out_value = NULL;
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fields[0].in_value = NULL;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].in_value = (uint8_t *)in;
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jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
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jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
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jtag_add_runtest(0, TAP_DRPAUSE);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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if (in)
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LOG_DEBUG("in: 0x%8.8x", *in);
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else
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LOG_ERROR("BUG: called with in == NULL");
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#endif
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return ERROR_OK;
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}
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/* clock the target, and read the databus
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* the *in pointer points to a buffer where elements of 'size' bytes
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* are stored in big (be == 1) or little (be == 0) endianness
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*/
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static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
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void *in, int size, int be)
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{
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int retval = ERROR_OK;
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struct scan_field fields[3];
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retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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fields[0].num_bits = 1;
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fields[0].out_value = NULL;
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fields[0].in_value = NULL;
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if (size == 4) {
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].in_value = in;
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} else {
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/* Discard irrelevant bits of the scan, making sure we don't write more
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* than size bytes to in */
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fields[1].num_bits = 32 - size * 8;
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fields[1].out_value = NULL;
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fields[1].in_value = NULL;
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fields[2].num_bits = size * 8;
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fields[2].out_value = NULL;
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fields[2].in_value = in;
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}
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jtag_add_dr_scan(jtag_info->tap, size == 4 ? 2 : 3, fields, TAP_DRPAUSE);
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jtag_add_callback4(arm7_9_endianness_callback,
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(jtag_callback_data_t)in,
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(jtag_callback_data_t)size,
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(jtag_callback_data_t)be,
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(jtag_callback_data_t)1);
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jtag_add_runtest(0, TAP_DRPAUSE);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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{
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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if (in)
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LOG_DEBUG("in: 0x%8.8x", *(uint32_t *)in);
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else
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LOG_ERROR("BUG: called with in == NULL");
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}
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#endif
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return ERROR_OK;
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}
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static void arm7tdmi_change_to_arm(struct target *target,
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uint32_t *r0, uint32_t *pc)
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{
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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struct arm_jtag *jtag_info = &arm7_9->jtag_info;
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/* save r0 before using it and put system in ARM state
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* to allow common handling of ARM and THUMB debugging */
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/* fetch STR r0, [r0] */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0);
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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/* nothing fetched, STR r0, [r0] in Execute (2) */
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arm7tdmi_clock_data_in(jtag_info, r0);
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/* MOV r0, r15 fetched, STR in Decode */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0);
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0);
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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/* nothing fetched, STR r0, [r0] in Execute (2) */
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arm7tdmi_clock_data_in(jtag_info, pc);
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/* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0);
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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/* nothing fetched, data for LDR r0, [PC, #0] */
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arm7tdmi_clock_out(jtag_info, 0x0, 0);
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/* nothing fetched, data from previous cycle is written to register */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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/* fetch BX */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0);
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/* NOP fetched, BX in Decode, MOV in Execute */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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/* NOP fetched, BX in Execute (1) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
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jtag_execute_queue();
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/* fix program counter:
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* MOV r0, r15 was the 4th instruction (+6)
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* reading PC in Thumb state gives address of instruction + 4
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*/
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*pc -= 0xa;
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}
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/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
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* roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
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*
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* The solution is to arrange for a large out/in scan in this loop and
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* and convert data afterwards.
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*/
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static void arm7tdmi_read_core_regs(struct target *target,
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uint32_t mask, uint32_t *core_regs[16])
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{
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int i;
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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struct arm_jtag *jtag_info = &arm7_9->jtag_info;
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/* STMIA r0-15, [r0] at debug speed
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* register values will start to appear on 4th DCLK
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*/
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arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0);
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/* fetch NOP, STM in DECODE stage */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* fetch NOP, STM in EXECUTE stage (1st cycle) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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for (i = 0; i <= 15; i++) {
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if (mask & (1 << i))
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/* nothing fetched, STM still in EXECUTE (1 + i cycle) */
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arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
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}
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}
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static void arm7tdmi_read_core_regs_target_buffer(struct target *target,
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uint32_t mask, void *buffer, int size)
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{
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int i;
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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struct arm_jtag *jtag_info = &arm7_9->jtag_info;
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int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
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uint32_t *buf_u32 = buffer;
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uint16_t *buf_u16 = buffer;
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uint8_t *buf_u8 = buffer;
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/* STMIA r0-15, [r0] at debug speed
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* register values will start to appear on 4th DCLK
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*/
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arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0);
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/* fetch NOP, STM in DECODE stage */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* fetch NOP, STM in EXECUTE stage (1st cycle) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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for (i = 0; i <= 15; i++) {
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/* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */
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if (mask & (1 << i)) {
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switch (size) {
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case 4:
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arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
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break;
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case 2:
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arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
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break;
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case 1:
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arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
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break;
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}
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}
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}
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}
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static void arm7tdmi_read_xpsr(struct target *target, uint32_t *xpsr, int spsr)
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{
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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struct arm_jtag *jtag_info = &arm7_9->jtag_info;
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/* MRS r0, cpsr */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0);
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/* STR r0, [r15] */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0);
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/* fetch NOP, STR in DECODE stage */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* fetch NOP, STR in EXECUTE stage (1st cycle) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* nothing fetched, STR still in EXECUTE (2nd cycle) */
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arm7tdmi_clock_data_in(jtag_info, xpsr);
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}
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static void arm7tdmi_write_xpsr(struct target *target, uint32_t xpsr, int spsr)
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{
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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struct arm_jtag *jtag_info = &arm7_9->jtag_info;
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LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
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/* MSR1 fetched */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0);
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/* MSR2 fetched, MSR1 in DECODE */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0);
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/* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0);
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/* nothing fetched, MSR1 in EXECUTE (2) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0);
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/* nothing fetched, MSR2 in EXECUTE (2) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* nothing fetched, MSR3 in EXECUTE (2) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* NOP fetched, MSR4 in EXECUTE (1) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* nothing fetched, MSR4 in EXECUTE (2) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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}
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static void arm7tdmi_write_xpsr_im8(struct target *target,
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uint8_t xpsr_im, int rot, int spsr)
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{
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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struct arm_jtag *jtag_info = &arm7_9->jtag_info;
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LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
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/* MSR fetched */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0);
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/* NOP fetched, MSR in DECODE */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* NOP fetched, MSR in EXECUTE (1) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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/* nothing fetched, MSR in EXECUTE (2) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
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}
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static void arm7tdmi_write_core_regs(struct target *target,
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uint32_t mask, uint32_t core_regs[16])
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{
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int i;
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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struct arm_jtag *jtag_info = &arm7_9->jtag_info;
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/* LDMIA r0-15, [r0] at debug speed
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* register values will start to appear on 4th DCLK
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*/
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arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0);
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/* fetch NOP, LDM in DECODE stage */
|
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arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
|
|
for (i = 0; i <= 15; i++) {
|
|
if (mask & (1 << i))
|
|
/* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
|
|
arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
|
|
}
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
}
|
|
|
|
static void arm7tdmi_load_word_regs(struct target *target, uint32_t mask)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed load-multiple into the pipeline */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0);
|
|
}
|
|
|
|
static void arm7tdmi_load_hword_reg(struct target *target, int num)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed load half-word into the pipeline */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0);
|
|
}
|
|
|
|
static void arm7tdmi_load_byte_reg(struct target *target, int num)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed load byte into the pipeline */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0);
|
|
}
|
|
|
|
static void arm7tdmi_store_word_regs(struct target *target, uint32_t mask)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed store-multiple into the pipeline */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0);
|
|
}
|
|
|
|
static void arm7tdmi_store_hword_reg(struct target *target, int num)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed store half-word into the pipeline */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0);
|
|
}
|
|
|
|
static void arm7tdmi_store_byte_reg(struct target *target, int num)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* put system-speed store byte into the pipeline */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0);
|
|
}
|
|
|
|
static void arm7tdmi_write_pc(struct target *target, uint32_t pc)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
|
|
/* LDMIA r0-15, [r0] at debug speed
|
|
* register values will start to appear on 4th DCLK
|
|
*/
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0);
|
|
/* fetch NOP, LDM in DECODE stage */
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
|
|
arm7tdmi_clock_out_inner(jtag_info, pc, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (4th cycle) */
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (5th cycle) */
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
|
|
}
|
|
|
|
static void arm7tdmi_branch_resume(struct target *target)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 1);
|
|
arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
|
|
}
|
|
|
|
static void arm7tdmi_branch_resume_thumb(struct target *target)
|
|
{
|
|
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
|
|
struct arm *arm = &arm7_9->arm;
|
|
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
|
|
struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
|
|
|
|
LOG_DEBUG("-");
|
|
|
|
/* LDMIA r0, [r0] at debug speed
|
|
* register values will start to appear on 4th DCLK
|
|
*/
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0);
|
|
|
|
/* fetch NOP, LDM in DECODE stage */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
/* fetch NOP, LDM in EXECUTE stage (1st cycle) */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
|
|
arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->pc->value, 0, 32) | 1, 0);
|
|
/* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
|
|
/* Branch and eXchange */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0);
|
|
|
|
embeddedice_read_reg(dbg_stat);
|
|
|
|
/* fetch NOP, BX in DECODE stage */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
|
|
/* target is now in Thumb state */
|
|
embeddedice_read_reg(dbg_stat);
|
|
|
|
/* fetch NOP, BX in EXECUTE stage (1st cycle) */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0);
|
|
|
|
/* target is now in Thumb state */
|
|
embeddedice_read_reg(dbg_stat);
|
|
|
|
/* load r0 value */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0);
|
|
/* fetch NOP, LDR in Decode */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
|
|
/* fetch NOP, LDR in Execute */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
|
|
/* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
|
|
arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), 0);
|
|
/* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
|
|
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0);
|
|
|
|
embeddedice_read_reg(dbg_stat);
|
|
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 1);
|
|
arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), 0);
|
|
}
|
|
|
|
static void arm7tdmi_build_reg_cache(struct target *target)
|
|
{
|
|
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
|
|
struct arm *arm = target_to_arm(target);
|
|
|
|
(*cache_p) = arm_build_reg_cache(target, arm);
|
|
}
|
|
|
|
static void arm7tdmi_free_reg_cache(struct target *target)
|
|
{
|
|
struct arm *arm = target_to_arm(target);
|
|
|
|
arm_free_reg_cache(arm);
|
|
}
|
|
|
|
int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
|
|
{
|
|
arm7tdmi_build_reg_cache(target);
|
|
arm_semihosting_init(target);
|
|
return ERROR_OK;
|
|
}
|
|
|
|
void arm7tdmi_deinit_target(struct target *target)
|
|
{
|
|
arm7tdmi_free_reg_cache(target);
|
|
}
|
|
|
|
int arm7tdmi_init_arch_info(struct target *target,
|
|
struct arm7_9_common *arm7_9, struct jtag_tap *tap)
|
|
{
|
|
/* prepare JTAG information for the new target */
|
|
arm7_9->jtag_info.tap = tap;
|
|
arm7_9->jtag_info.scann_size = 4;
|
|
|
|
/* register arch-specific functions */
|
|
arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
|
|
arm7_9->change_to_arm = arm7tdmi_change_to_arm;
|
|
arm7_9->read_core_regs = arm7tdmi_read_core_regs;
|
|
arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
|
|
arm7_9->read_xpsr = arm7tdmi_read_xpsr;
|
|
|
|
arm7_9->write_xpsr = arm7tdmi_write_xpsr;
|
|
arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
|
|
arm7_9->write_core_regs = arm7tdmi_write_core_regs;
|
|
|
|
arm7_9->load_word_regs = arm7tdmi_load_word_regs;
|
|
arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
|
|
arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
|
|
|
|
arm7_9->store_word_regs = arm7tdmi_store_word_regs;
|
|
arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
|
|
arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
|
|
|
|
arm7_9->write_pc = arm7tdmi_write_pc;
|
|
arm7_9->branch_resume = arm7tdmi_branch_resume;
|
|
arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
|
|
|
|
arm7_9->enable_single_step = arm7_9_enable_eice_step;
|
|
arm7_9->disable_single_step = arm7_9_disable_eice_step;
|
|
|
|
arm7_9->write_memory = arm7_9_write_memory;
|
|
arm7_9->bulk_write_memory = arm7_9_bulk_write_memory;
|
|
|
|
arm7_9->post_debug_entry = NULL;
|
|
|
|
arm7_9->pre_restore_context = NULL;
|
|
|
|
/* initialize arch-specific breakpoint handling */
|
|
arm7_9->arm_bkpt = 0xdeeedeee;
|
|
arm7_9->thumb_bkpt = 0xdeee;
|
|
|
|
arm7_9->dbgreq_adjust_pc = 2;
|
|
|
|
arm7_9_init_arch_info(target, arm7_9);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp)
|
|
{
|
|
struct arm7_9_common *arm7_9;
|
|
|
|
arm7_9 = calloc(1, sizeof(struct arm7_9_common));
|
|
arm7tdmi_init_arch_info(target, arm7_9, target->tap);
|
|
arm7_9->arm.arch = ARM_ARCH_V4;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
/** Holds methods for ARM7TDMI targets. */
|
|
struct target_type arm7tdmi_target = {
|
|
.name = "arm7tdmi",
|
|
|
|
.poll = arm7_9_poll,
|
|
.arch_state = arm_arch_state,
|
|
|
|
.target_request_data = arm7_9_target_request_data,
|
|
|
|
.halt = arm7_9_halt,
|
|
.resume = arm7_9_resume,
|
|
.step = arm7_9_step,
|
|
|
|
.assert_reset = arm7_9_assert_reset,
|
|
.deassert_reset = arm7_9_deassert_reset,
|
|
.soft_reset_halt = arm7_9_soft_reset_halt,
|
|
|
|
.get_gdb_arch = arm_get_gdb_arch,
|
|
.get_gdb_reg_list = arm_get_gdb_reg_list,
|
|
|
|
.read_memory = arm7_9_read_memory,
|
|
.write_memory = arm7_9_write_memory_opt,
|
|
|
|
.checksum_memory = arm_checksum_memory,
|
|
.blank_check_memory = arm_blank_check_memory,
|
|
|
|
.run_algorithm = armv4_5_run_algorithm,
|
|
|
|
.add_breakpoint = arm7_9_add_breakpoint,
|
|
.remove_breakpoint = arm7_9_remove_breakpoint,
|
|
.add_watchpoint = arm7_9_add_watchpoint,
|
|
.remove_watchpoint = arm7_9_remove_watchpoint,
|
|
|
|
.commands = arm7_9_command_handlers,
|
|
.target_create = arm7tdmi_target_create,
|
|
.init_target = arm7tdmi_init_target,
|
|
.deinit_target = arm7tdmi_deinit_target,
|
|
.examine = arm7_9_examine,
|
|
.check_reset = arm7_9_check_reset,
|
|
};
|