238 lines
7.7 KiB
C
238 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2009 by David Brownell
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*/
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#ifndef OPENOCD_TARGET_ARM_DPM_H
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#define OPENOCD_TARGET_ARM_DPM_H
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/**
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* @file
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* This is the interface to the Debug Programmers Model for ARMv6 and
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* ARMv7 processors. ARMv6 processors (such as ARM11xx implementations)
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* introduced a model which became part of the ARMv7-AR architecture
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* which is most familiar through the Cortex-A series parts. While
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* specific details differ (like how to write the instruction register),
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* the high level models easily support shared code because those
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* registers are compatible.
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*/
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struct dpm_bpwp {
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unsigned number;
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uint32_t address;
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uint32_t control;
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/* true if hardware state needs flushing */
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bool dirty;
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};
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struct dpm_bp {
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struct breakpoint *bp;
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struct dpm_bpwp bpwp;
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};
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struct dpm_wp {
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struct watchpoint *wp;
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struct dpm_bpwp bpwp;
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};
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/**
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* This wraps an implementation of DPM primitives. Each interface
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* provider supplies a structure like this, which is the glue between
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* upper level code and the lower level hardware access.
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*
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* It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
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* support for CPU register access.
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*/
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struct arm_dpm {
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struct arm *arm;
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/** Cache of DIDR */
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uint64_t didr;
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/** Invoke before a series of instruction operations */
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int (*prepare)(struct arm_dpm *dpm);
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/** Invoke after a series of instruction operations */
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int (*finish)(struct arm_dpm *dpm);
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/** Runs one instruction. */
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int (*instr_execute)(struct arm_dpm *dpm, uint32_t opcode);
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/* WRITE TO CPU */
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/** Runs one instruction, writing data to DCC before execution. */
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int (*instr_write_data_dcc)(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t data);
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int (*instr_write_data_dcc_64)(struct arm_dpm *dpm,
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uint32_t opcode, uint64_t data);
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/** Runs one instruction, writing data to R0 before execution. */
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int (*instr_write_data_r0)(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t data);
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/** Runs one instruction, writing data to R0 before execution. */
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int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
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uint32_t opcode, uint64_t data);
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/** Optional core-specific operation invoked after CPSR writes. */
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int (*instr_cpsr_sync)(struct arm_dpm *dpm);
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/* READ FROM CPU */
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/** Runs one instruction, reading data from dcc after execution. */
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int (*instr_read_data_dcc)(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t *data);
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int (*instr_read_data_dcc_64)(struct arm_dpm *dpm,
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uint32_t opcode, uint64_t *data);
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/** Runs one instruction, reading data from r0 after execution. */
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int (*instr_read_data_r0)(struct arm_dpm *dpm,
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uint32_t opcode, uint32_t *data);
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int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
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uint32_t opcode, uint64_t *data);
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struct reg *(*arm_reg_current)(struct arm *arm,
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unsigned regnum);
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/* BREAKPOINT/WATCHPOINT SUPPORT */
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/**
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* Enables one breakpoint or watchpoint by writing to the
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* hardware registers. The specified breakpoint/watchpoint
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* must currently be disabled. Indices 0..15 are used for
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* breakpoints; indices 16..31 are for watchpoints.
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*/
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int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
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uint32_t addr, uint32_t control);
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/**
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* Disables one breakpoint or watchpoint by clearing its
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* hardware control registers. Indices are the same ones
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* accepted by bpwp_enable().
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*/
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int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
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/* The breakpoint and watchpoint arrays are private to the
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* DPM infrastructure. There are nbp indices in the dbp
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* array. There are nwp indices in the dwp array.
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*/
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unsigned nbp;
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unsigned nwp;
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struct dpm_bp *dbp;
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struct dpm_wp *dwp;
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/**
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* Target dependent watchpoint address.
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* Either the address of the instruction which triggered a watchpoint
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* or the memory address whose access triggered a watchpoint.
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*/
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target_addr_t wp_addr;
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/** Recent value of DSCR. */
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uint32_t dscr;
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/** Recent exception level on armv8 */
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unsigned int last_el;
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/* FIXME -- read/write DCSR methods and symbols */
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};
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int arm_dpm_setup(struct arm_dpm *dpm);
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int arm_dpm_initialize(struct arm_dpm *dpm);
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int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
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int arm_dpm_read_current_registers(struct arm_dpm *dpm);
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int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
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int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
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void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar);
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/* DSCR bits; see ARMv7a arch spec section C10.3.1.
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* Not all v7 bits are valid in v6.
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*/
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#define DSCR_CORE_HALTED (0x1 << 0)
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#define DSCR_CORE_RESTARTED (0x1 << 1)
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#define DSCR_ENTRY_MASK (0xF << 2)
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#define DSCR_STICKY_ABORT_PRECISE (0x1 << 6)
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#define DSCR_STICKY_ABORT_IMPRECISE (0x1 << 7)
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#define DSCR_STICKY_UNDEFINED (0x1 << 8)
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#define DSCR_DBG_NOPWRDWN (0x1 << 9) /* v6 only */
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#define DSCR_DBG_ACK (0x1 << 10)
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#define DSCR_INT_DIS (0x1 << 11)
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#define DSCR_CP14_USR_COMMS (0x1 << 12)
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#define DSCR_ITR_EN (0x1 << 13)
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#define DSCR_HALT_DBG_MODE (0x1 << 14)
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#define DSCR_MON_DBG_MODE (0x1 << 15)
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#define DSCR_SEC_PRIV_INVASV_DIS (0x1 << 16)
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#define DSCR_SEC_PRIV_NINVASV_DIS (0x1 << 17)
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#define DSCR_NON_SECURE (0x1 << 18)
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#define DSCR_DSCRD_IMPRECISE_ABORT (0x1 << 19)
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#define DSCR_EXT_DCC_MASK (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */
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#define DSCR_INSTR_COMP (0x1 << 24)
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#define DSCR_PIPE_ADVANCE (0x1 << 25)
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#define DSCR_DTRTX_FULL_LATCHED (0x1 << 26)
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#define DSCR_DTRRX_FULL_LATCHED (0x1 << 27) /* bit 28 is reserved */
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#define DSCR_DTR_TX_FULL (0x1 << 29)
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#define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
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#define DSCR_ENTRY(dscr) ((dscr) & 0x3f)
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#define DSCR_RUN_MODE(dscr) ((dscr) & 0x03)
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/* Methods of entry into debug mode */
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#define DSCR_ENTRY_HALT_REQ (0x03)
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#define DSCR_ENTRY_BREAKPOINT (0x07)
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#define DSCR_ENTRY_IMPRECISE_WATCHPT (0x0B)
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#define DSCR_ENTRY_BKPT_INSTR (0x0F)
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#define DSCR_ENTRY_EXT_DBG_REQ (0x13)
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#define DSCR_ENTRY_VECT_CATCH (0x17)
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#define DSCR_ENTRY_D_SIDE_ABORT (0x1B) /* v6 only */
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#define DSCR_ENTRY_I_SIDE_ABORT (0x1F) /* v6 only */
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#define DSCR_ENTRY_OS_UNLOCK (0x23)
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#define DSCR_ENTRY_PRECISE_WATCHPT (0x2B)
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/* DTR modes */
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#define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
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#define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
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#define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
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/* DRCR (debug run control register) bits */
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#define DRCR_HALT (1 << 0)
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#define DRCR_RESTART (1 << 1)
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#define DRCR_CLEAR_EXCEPTIONS (1 << 2)
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void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
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/* PRCR (Device Power-down and Reset Control Register) bits */
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#define PRCR_DEBUG_NO_POWER_DOWN (1 << 0)
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#define PRCR_WARM_RESET (1 << 1)
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#define PRCR_HOLD_NON_DEBUG_RESET (1 << 2)
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/* PRSR (Device Power-down and Reset Status Register) bits */
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#define PRSR_POWERUP_STATUS (1 << 0)
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#define PRSR_STICKY_POWERDOWN_STATUS (1 << 1)
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#define PRSR_RESET_STATUS (1 << 2)
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#define PRSR_STICKY_RESET_STATUS (1 << 3)
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#define PRSR_HALTED (1 << 4) /* v7.1 Debug only */
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#define PRSR_OSLK (1 << 5) /* v7.1 Debug only */
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#define PRSR_DLK (1 << 6) /* v7.1 Debug only */
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/* OSLSR (OS Lock Status Register) bits */
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#define OSLSR_OSLM0 (1 << 0)
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#define OSLSR_OSLK (1 << 1)
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#define OSLSR_NTT (1 << 2)
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#define OSLSR_OSLM1 (1 << 3)
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#define OSLSR_OSLM (OSLSR_OSLM0|OSLSR_OSLM1)
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#endif /* OPENOCD_TARGET_ARM_DPM_H */
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