39 lines
1.7 KiB
C
39 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2009 by Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARMV4_5_H
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#define OPENOCD_TARGET_ARMV4_5_H
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/* This stuff "knows" that its callers aren't talking
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* to microcontroller profile (current Cortex-M) parts.
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* We want to phase it out so core code can be shared.
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*/
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/* OBSOLETE, DO NOT USE IN NEW CODE! The "number" of an arm_mode is an
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* index into the armv4_5_core_reg_map array. Its remaining users are
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* remnants which could as easily walk * the register cache directly as
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* use the expensive ARMV4_5_CORE_REG_MODE() macro.
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*/
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int arm_mode_to_number(enum arm_mode mode);
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enum arm_mode armv4_5_number_to_mode(int number);
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extern const int armv4_5_core_reg_map[9][17];
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#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
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(cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]])
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/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
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enum { ARMV4_5_CPSR = 31, };
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#endif /* OPENOCD_TARGET_ARMV4_5_H */
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