148 lines
4.6 KiB
C
148 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2015 Oleksij Rempel *
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* linux@rempel-privat.de *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARM7A_CACHE_L2X_H
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#define OPENOCD_TARGET_ARM7A_CACHE_L2X_H
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#define L2X0_CACHE_LINE_SIZE 32
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/* source: linux/arch/arm/include/asm/hardware/cache-l2x0.h */
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#define L2X0_CACHE_ID 0x000
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#define L2X0_CACHE_TYPE 0x004
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#define L2X0_CTRL 0x100
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#define L2X0_AUX_CTRL 0x104
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#define L2X0_TAG_LATENCY_CTRL 0x108
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#define L2X0_DATA_LATENCY_CTRL 0x10C
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#define L2X0_EVENT_CNT_CTRL 0x200
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#define L2X0_EVENT_CNT1_CFG 0x204
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#define L2X0_EVENT_CNT0_CFG 0x208
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#define L2X0_EVENT_CNT1_VAL 0x20C
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#define L2X0_EVENT_CNT0_VAL 0x210
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#define L2X0_INTR_MASK 0x214
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#define L2X0_MASKED_INTR_STAT 0x218
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#define L2X0_RAW_INTR_STAT 0x21C
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#define L2X0_INTR_CLEAR 0x220
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#define L2X0_CACHE_SYNC 0x730
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#define L2X0_DUMMY_REG 0x740
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#define L2X0_INV_LINE_PA 0x770
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#define L2X0_INV_WAY 0x77C
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#define L2X0_CLEAN_LINE_PA 0x7B0
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#define L2X0_CLEAN_LINE_IDX 0x7B8
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#define L2X0_CLEAN_WAY 0x7BC
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#define L2X0_CLEAN_INV_LINE_PA 0x7F0
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#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
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#define L2X0_CLEAN_INV_WAY 0x7FC
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/*
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* The lockdown registers repeat 8 times for L310, the L210 has only one
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* D and one I lockdown register at 0x0900 and 0x0904.
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*/
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#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
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#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
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#define L2X0_LOCKDOWN_STRIDE 0x08
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#define L2X0_ADDR_FILTER_START 0xC00
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#define L2X0_ADDR_FILTER_END 0xC04
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#define L2X0_TEST_OPERATION 0xF00
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#define L2X0_LINE_DATA 0xF10
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#define L2X0_LINE_TAG 0xF30
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#define L2X0_DEBUG_CTRL 0xF40
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#define L2X0_PREFETCH_CTRL 0xF60
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#define L2X0_POWER_CTRL 0xF80
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#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
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#define L2X0_STNDBY_MODE_EN (1 << 0)
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/* Registers shifts and masks */
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#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
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#define L2X0_CACHE_ID_PART_L210 (1 << 6)
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#define L2X0_CACHE_ID_PART_L310 (3 << 6)
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#define L2X0_CACHE_ID_RTL_MASK 0x3f
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#define L2X0_CACHE_ID_RTL_R0P0 0x0
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#define L2X0_CACHE_ID_RTL_R1P0 0x2
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#define L2X0_CACHE_ID_RTL_R2P0 0x4
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#define L2X0_CACHE_ID_RTL_R3P0 0x5
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#define L2X0_CACHE_ID_RTL_R3P1 0x6
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#define L2X0_CACHE_ID_RTL_R3P2 0x8
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#define L2X0_AUX_CTRL_MASK 0xc0000fff
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#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
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#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
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#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
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#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
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#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
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#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
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#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
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#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
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#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
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#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
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#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
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#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
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#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
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#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
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#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28
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#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
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#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
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#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
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#define L2X0_LATENCY_CTRL_RD_SHIFT 4
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#define L2X0_LATENCY_CTRL_WR_SHIFT 8
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#define L2X0_ADDR_FILTER_EN 1
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#define L2X0_CTRL_EN 1
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#define L2X0_WAY_SIZE_SHIFT 3
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struct l2x0_regs {
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unsigned long phy_base;
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unsigned long aux_ctrl;
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/*
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* Whether the following registers need to be saved/restored
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* depends on platform
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*/
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unsigned long tag_latency;
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unsigned long data_latency;
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unsigned long filter_start;
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unsigned long filter_end;
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unsigned long prefetch_ctrl;
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unsigned long pwr_ctrl;
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unsigned long ctrl;
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unsigned long aux2_ctrl;
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};
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struct outer_cache_fns {
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void (*inv_range)(unsigned long, unsigned long);
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void (*clean_range)(unsigned long, unsigned long);
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void (*flush_range)(unsigned long, unsigned long);
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void (*flush_all)(void);
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void (*disable)(void);
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void (*resume)(void);
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/* This is an ARM L2C thing */
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void (*write_sec)(unsigned long, unsigned);
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void (*configure)(const struct l2x0_regs *);
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};
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struct l2c_init_data {
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const char *type;
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unsigned way_size_0;
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unsigned num_lock;
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void (*enable)(uint32_t, uint32_t, unsigned);
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void (*fixup)(uint32_t, uint32_t, struct outer_cache_fns *);
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void (*save)(uint32_t);
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void (*configure)(uint32_t);
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struct outer_cache_fns outer_cache;
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};
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extern const struct command_registration arm7a_l2x_cache_command_handler[];
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int armv7a_l2x_cache_flush_virt(struct target *target, target_addr_t virt,
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uint32_t size);
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int arm7a_l2x_flush_all_data(struct target *target);
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#endif /* OPENOCD_TARGET_ARM7A_CACHE_L2X_H */
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