350 lines
9.2 KiB
C
350 lines
9.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ARMV7M_H
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#define OPENOCD_TARGET_ARMV7M_H
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#include "arm.h"
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#include "armv7m_trace.h"
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struct adiv5_ap;
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extern const int armv7m_psp_reg_map[];
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extern const int armv7m_msp_reg_map[];
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const char *armv7m_exception_string(int number);
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/* Cortex-M DCRSR.REGSEL selectors */
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enum {
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ARMV7M_REGSEL_R0,
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ARMV7M_REGSEL_R1,
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ARMV7M_REGSEL_R2,
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ARMV7M_REGSEL_R3,
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ARMV7M_REGSEL_R4,
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ARMV7M_REGSEL_R5,
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ARMV7M_REGSEL_R6,
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ARMV7M_REGSEL_R7,
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ARMV7M_REGSEL_R8,
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ARMV7M_REGSEL_R9,
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ARMV7M_REGSEL_R10,
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ARMV7M_REGSEL_R11,
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ARMV7M_REGSEL_R12,
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ARMV7M_REGSEL_R13,
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ARMV7M_REGSEL_R14,
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ARMV7M_REGSEL_PC = 15,
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ARMV7M_REGSEL_xPSR = 16,
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ARMV7M_REGSEL_MSP,
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ARMV7M_REGSEL_PSP,
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ARMV8M_REGSEL_MSP_NS = 0x18,
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ARMV8M_REGSEL_PSP_NS,
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ARMV8M_REGSEL_MSP_S,
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ARMV8M_REGSEL_PSP_S,
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ARMV8M_REGSEL_MSPLIM_S,
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ARMV8M_REGSEL_PSPLIM_S,
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ARMV8M_REGSEL_MSPLIM_NS,
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ARMV8M_REGSEL_PSPLIM_NS,
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ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
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ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S = 0x22,
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ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS = 0x23,
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ARMV7M_REGSEL_FPSCR = 0x21,
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/* 32bit Floating-point registers */
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ARMV7M_REGSEL_S0 = 0x40,
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ARMV7M_REGSEL_S1,
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ARMV7M_REGSEL_S2,
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ARMV7M_REGSEL_S3,
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ARMV7M_REGSEL_S4,
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ARMV7M_REGSEL_S5,
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ARMV7M_REGSEL_S6,
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ARMV7M_REGSEL_S7,
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ARMV7M_REGSEL_S8,
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ARMV7M_REGSEL_S9,
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ARMV7M_REGSEL_S10,
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ARMV7M_REGSEL_S11,
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ARMV7M_REGSEL_S12,
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ARMV7M_REGSEL_S13,
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ARMV7M_REGSEL_S14,
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ARMV7M_REGSEL_S15,
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ARMV7M_REGSEL_S16,
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ARMV7M_REGSEL_S17,
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ARMV7M_REGSEL_S18,
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ARMV7M_REGSEL_S19,
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ARMV7M_REGSEL_S20,
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ARMV7M_REGSEL_S21,
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ARMV7M_REGSEL_S22,
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ARMV7M_REGSEL_S23,
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ARMV7M_REGSEL_S24,
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ARMV7M_REGSEL_S25,
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ARMV7M_REGSEL_S26,
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ARMV7M_REGSEL_S27,
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ARMV7M_REGSEL_S28,
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ARMV7M_REGSEL_S29,
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ARMV7M_REGSEL_S30,
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ARMV7M_REGSEL_S31,
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};
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/* offsets into armv7m core register cache */
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enum {
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/* for convenience, the first set of indices match
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* the Cortex-M DCRSR.REGSEL selectors
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*/
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ARMV7M_R0 = ARMV7M_REGSEL_R0,
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ARMV7M_R1 = ARMV7M_REGSEL_R1,
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ARMV7M_R2 = ARMV7M_REGSEL_R2,
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ARMV7M_R3 = ARMV7M_REGSEL_R3,
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ARMV7M_R4 = ARMV7M_REGSEL_R4,
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ARMV7M_R5 = ARMV7M_REGSEL_R5,
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ARMV7M_R6 = ARMV7M_REGSEL_R6,
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ARMV7M_R7 = ARMV7M_REGSEL_R7,
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ARMV7M_R8 = ARMV7M_REGSEL_R8,
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ARMV7M_R9 = ARMV7M_REGSEL_R9,
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ARMV7M_R10 = ARMV7M_REGSEL_R10,
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ARMV7M_R11 = ARMV7M_REGSEL_R11,
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ARMV7M_R12 = ARMV7M_REGSEL_R12,
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ARMV7M_R13 = ARMV7M_REGSEL_R13,
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ARMV7M_R14 = ARMV7M_REGSEL_R14,
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ARMV7M_PC = ARMV7M_REGSEL_PC,
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ARMV7M_xPSR = ARMV7M_REGSEL_xPSR,
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ARMV7M_MSP = ARMV7M_REGSEL_MSP,
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ARMV7M_PSP = ARMV7M_REGSEL_PSP,
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/* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
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/* A block of container and contained registers follows:
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* THE ORDER IS IMPORTANT to the end of the block ! */
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/* working register for packing/unpacking special regs, hidden from gdb */
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ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
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/* WARNING: If you use armv7m_write_core_reg() on one of 4 following
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* special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
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* cache only and are not flushed to CPU HW register.
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* To trigger write to CPU HW register, add
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* armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
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*/
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ARMV7M_PRIMASK,
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ARMV7M_BASEPRI,
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ARMV7M_FAULTMASK,
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ARMV7M_CONTROL,
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/* The end of block of container and contained registers */
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/* ARMv8-M specific registers */
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ARMV8M_MSP_NS,
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ARMV8M_PSP_NS,
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ARMV8M_MSP_S,
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ARMV8M_PSP_S,
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ARMV8M_MSPLIM_S,
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ARMV8M_PSPLIM_S,
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ARMV8M_MSPLIM_NS,
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ARMV8M_PSPLIM_NS,
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/* A block of container and contained registers follows:
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* THE ORDER IS IMPORTANT to the end of the block ! */
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ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S,
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ARMV8M_PRIMASK_S,
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ARMV8M_BASEPRI_S,
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ARMV8M_FAULTMASK_S,
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ARMV8M_CONTROL_S,
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/* The end of block of container and contained registers */
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/* A block of container and contained registers follows:
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* THE ORDER IS IMPORTANT to the end of the block ! */
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ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS,
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ARMV8M_PRIMASK_NS,
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ARMV8M_BASEPRI_NS,
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ARMV8M_FAULTMASK_NS,
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ARMV8M_CONTROL_NS,
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/* The end of block of container and contained registers */
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/* 64bit Floating-point registers */
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ARMV7M_D0,
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ARMV7M_D1,
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ARMV7M_D2,
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ARMV7M_D3,
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ARMV7M_D4,
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ARMV7M_D5,
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ARMV7M_D6,
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ARMV7M_D7,
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ARMV7M_D8,
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ARMV7M_D9,
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ARMV7M_D10,
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ARMV7M_D11,
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ARMV7M_D12,
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ARMV7M_D13,
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ARMV7M_D14,
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ARMV7M_D15,
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/* Floating-point status register */
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ARMV7M_FPSCR,
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/* for convenience add registers' block delimiters */
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ARMV7M_LAST_REG,
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ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
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ARMV7M_CORE_LAST_REG = ARMV7M_xPSR,
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ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
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ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
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ARMV8M_FIRST_REG = ARMV8M_MSP_NS,
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ARMV8M_LAST_REG = ARMV8M_CONTROL_NS,
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};
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enum {
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FP_NONE = 0,
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FPV4_SP,
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FPV5_SP,
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FPV5_DP,
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};
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#define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
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#define ARMV7M_COMMON_MAGIC 0x2A452A45U
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struct armv7m_common {
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unsigned int common_magic;
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struct arm arm;
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int exception_number;
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/* AP this processor is connected to in the DAP */
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struct adiv5_ap *debug_ap;
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int fp_feature;
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uint32_t demcr;
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/* hla_target uses a high level adapter that does not support all functions */
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bool is_hla_target;
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struct armv7m_trace_config trace_config;
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/* Direct processor core register read and writes */
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int (*load_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t *value);
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int (*store_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t value);
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int (*examine_debug_reason)(struct target *target);
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int (*post_debug_entry)(struct target *target);
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void (*pre_restore_context)(struct target *target);
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};
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static inline bool is_armv7m(const struct armv7m_common *armv7m)
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{
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return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
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}
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/**
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* @returns the pointer to the target specific struct
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* without matching a magic number.
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* Use in target specific service routines, where the correct
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* type of arch_info is certain.
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*/
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static inline struct armv7m_common *
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target_to_armv7m(struct target *target)
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{
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return container_of(target->arch_info, struct armv7m_common, arm);
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}
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/**
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* @returns the pointer to the target specific struct
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* or NULL if the magic number does not match.
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* Use in a flash driver or any place where mismatch of the arch_info
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* type can happen.
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*/
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static inline struct armv7m_common *
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target_to_armv7m_safe(struct target *target)
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{
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if (!target)
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return NULL;
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if (!target->arch_info)
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return NULL;
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/* Check the parent type first to prevent peeking memory too far
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* from arch_info pointer */
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if (!is_arm(target_to_arm(target)))
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return NULL;
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struct armv7m_common *armv7m = target_to_armv7m(target);
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if (!is_armv7m(armv7m))
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return NULL;
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return armv7m;
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}
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struct armv7m_algorithm {
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unsigned int common_magic;
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enum arm_mode core_mode;
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uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
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};
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struct reg_cache *armv7m_build_reg_cache(struct target *target);
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void armv7m_free_reg_cache(struct target *target);
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enum armv7m_mode armv7m_number_to_mode(int number);
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int armv7m_mode_to_number(enum armv7m_mode mode);
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int armv7m_arch_state(struct target *target);
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int armv7m_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size,
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enum target_register_class reg_class);
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int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
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int armv7m_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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int timeout_ms, void *arch_info);
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int armv7m_start_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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void *arch_info);
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int armv7m_wait_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t exit_point, int timeout_ms,
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void *arch_info);
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int armv7m_invalidate_core_regs(struct target *target);
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int armv7m_restore_context(struct target *target);
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uint32_t armv7m_map_id_to_regsel(unsigned int arm_reg_id);
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bool armv7m_map_reg_packing(unsigned int arm_reg_id,
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unsigned int *reg32_id, uint32_t *offset);
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int armv7m_checksum_memory(struct target *target,
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target_addr_t address, uint32_t count, uint32_t *checksum);
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int armv7m_blank_check_memory(struct target *target,
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struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
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int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
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extern const struct command_registration armv7m_command_handlers[];
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#endif /* OPENOCD_TARGET_ARMV7M_H */
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