110 lines
2.9 KiB
C
110 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2009 by Dirk Behme *
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* dirk.behme@gmail.com - copy from cortex_m3 *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_CORTEX_A_H
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#define OPENOCD_TARGET_CORTEX_A_H
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#include "armv7a.h"
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#define CORTEX_A_COMMON_MAGIC 0x411fc082U
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#define CORTEX_A5_PARTNUM 0xc05
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#define CORTEX_A7_PARTNUM 0xc07
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#define CORTEX_A8_PARTNUM 0xc08
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#define CORTEX_A9_PARTNUM 0xc09
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#define CORTEX_A15_PARTNUM 0xc0f
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#define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
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#define CORTEX_A_MIDR_PARTNUM_SHIFT 4
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#define CPUDBG_CPUID 0xD00
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#define CPUDBG_CTYPR 0xD04
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#define CPUDBG_TTYPR 0xD0C
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#define CPUDBG_LOCKACCESS 0xFB0
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#define CPUDBG_LOCKSTATUS 0xFB4
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#define CPUDBG_OSLAR_LK_MASK (1 << 1)
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#define BRP_NORMAL 0
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#define BRP_CONTEXT 1
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#define CORTEX_A_PADDRDBG_CPU_SHIFT 13
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enum cortex_a_isrmasking_mode {
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CORTEX_A_ISRMASK_OFF,
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CORTEX_A_ISRMASK_ON,
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};
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enum cortex_a_dacrfixup_mode {
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CORTEX_A_DACRFIXUP_OFF,
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CORTEX_A_DACRFIXUP_ON
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};
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struct cortex_a_brp {
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bool used;
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int type;
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uint32_t value;
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uint32_t control;
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uint8_t brpn;
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};
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struct cortex_a_wrp {
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bool used;
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uint32_t value;
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uint32_t control;
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uint8_t wrpn;
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};
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struct cortex_a_common {
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unsigned int common_magic;
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struct armv7a_common armv7a_common;
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/* Context information */
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uint32_t cpudbg_dscr;
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/* Saved cp15 registers */
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uint32_t cp15_control_reg;
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/* latest cp15 register value written and cpsr processor mode */
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uint32_t cp15_control_reg_curr;
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/* auxiliary control reg */
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uint32_t cp15_aux_control_reg;
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/* DACR */
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uint32_t cp15_dacr_reg;
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enum arm_mode curr_mode;
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/* Breakpoint register pairs */
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int brp_num_context;
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int brp_num;
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int brp_num_available;
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struct cortex_a_brp *brp_list;
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int wrp_num;
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int wrp_num_available;
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struct cortex_a_wrp *wrp_list;
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uint32_t cpuid;
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uint32_t didr;
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enum cortex_a_isrmasking_mode isrmasking_mode;
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enum cortex_a_dacrfixup_mode dacrfixup_mode;
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};
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static inline struct cortex_a_common *
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target_to_cortex_a(struct target *target)
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{
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return container_of(target->arch_info, struct cortex_a_common, armv7a_common.arm);
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}
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#endif /* OPENOCD_TARGET_CORTEX_A_H */
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