321 lines
9.0 KiB
C
321 lines
9.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2005 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2006 by Magnus Lundin *
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* lundin@mlu.mine.nu *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_CORTEX_M_H
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#define OPENOCD_TARGET_CORTEX_M_H
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#include "armv7m.h"
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#include "helper/bits.h"
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#define CORTEX_M_COMMON_MAGIC 0x1A451A45U
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#define SYSTEM_CONTROL_BASE 0x400FE000
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#define ITM_TER0 0xE0000E00
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#define ITM_TPR 0xE0000E40
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#define ITM_TCR 0xE0000E80
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#define ITM_TCR_ITMENA_BIT BIT(0)
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#define ITM_TCR_BUSY_BIT BIT(23)
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#define ITM_LAR 0xE0000FB0
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#define ITM_LAR_KEY 0xC5ACCE55
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#define CPUID 0xE000ED00
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#define ARM_CPUID_PARTNO_POS 4
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#define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
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enum cortex_m_partno {
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CORTEX_M_PARTNO_INVALID,
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CORTEX_M0_PARTNO = 0xC20,
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CORTEX_M1_PARTNO = 0xC21,
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CORTEX_M3_PARTNO = 0xC23,
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CORTEX_M4_PARTNO = 0xC24,
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CORTEX_M7_PARTNO = 0xC27,
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CORTEX_M0P_PARTNO = 0xC60,
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CORTEX_M23_PARTNO = 0xD20,
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CORTEX_M33_PARTNO = 0xD21,
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CORTEX_M35P_PARTNO = 0xD31,
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CORTEX_M55_PARTNO = 0xD22,
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};
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/* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
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#define CORTEX_M_F_HAS_FPV4 BIT(0)
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#define CORTEX_M_F_HAS_FPV5 BIT(1)
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#define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
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struct cortex_m_part_info {
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enum cortex_m_partno partno;
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const char *name;
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enum arm_arch arch;
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uint32_t flags;
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};
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/* Debug Control Block */
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#define DCB_DHCSR 0xE000EDF0
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#define DCB_DCRSR 0xE000EDF4
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#define DCB_DCRDR 0xE000EDF8
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#define DCB_DEMCR 0xE000EDFC
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#define DCB_DSCSR 0xE000EE08
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#define DCRSR_WNR BIT(16)
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#define DWT_CTRL 0xE0001000
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#define DWT_CYCCNT 0xE0001004
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#define DWT_PCSR 0xE000101C
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#define DWT_COMP0 0xE0001020
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#define DWT_MASK0 0xE0001024
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#define DWT_FUNCTION0 0xE0001028
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#define DWT_DEVARCH 0xE0001FBC
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#define DWT_DEVARCH_ARMV8M 0x101A02
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#define FP_CTRL 0xE0002000
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#define FP_REMAP 0xE0002004
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#define FP_COMP0 0xE0002008
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#define FP_COMP1 0xE000200C
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#define FP_COMP2 0xE0002010
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#define FP_COMP3 0xE0002014
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#define FP_COMP4 0xE0002018
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#define FP_COMP5 0xE000201C
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#define FP_COMP6 0xE0002020
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#define FP_COMP7 0xE0002024
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#define FPU_CPACR 0xE000ED88
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#define FPU_FPCCR 0xE000EF34
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#define FPU_FPCAR 0xE000EF38
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#define FPU_FPDSCR 0xE000EF3C
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#define TPIU_SSPSR 0xE0040000
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#define TPIU_CSPSR 0xE0040004
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#define TPIU_ACPR 0xE0040010
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#define TPIU_SPPR 0xE00400F0
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#define TPIU_FFSR 0xE0040300
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#define TPIU_FFCR 0xE0040304
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#define TPIU_FSCR 0xE0040308
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/* Maximum SWO prescaler value. */
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#define TPIU_ACPR_MAX_SWOSCALER 0x1fff
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/* DCB_DHCSR bit and field definitions */
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#define DBGKEY (0xA05Ful << 16)
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#define C_DEBUGEN BIT(0)
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#define C_HALT BIT(1)
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#define C_STEP BIT(2)
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#define C_MASKINTS BIT(3)
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#define S_REGRDY BIT(16)
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#define S_HALT BIT(17)
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#define S_SLEEP BIT(18)
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#define S_LOCKUP BIT(19)
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#define S_RETIRE_ST BIT(24)
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#define S_RESET_ST BIT(25)
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/* DCB_DEMCR bit and field definitions */
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#define TRCENA BIT(24)
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#define VC_HARDERR BIT(10)
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#define VC_INTERR BIT(9)
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#define VC_BUSERR BIT(8)
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#define VC_STATERR BIT(7)
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#define VC_CHKERR BIT(6)
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#define VC_NOCPERR BIT(5)
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#define VC_MMERR BIT(4)
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#define VC_CORERESET BIT(0)
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/* DCB_DSCSR bit and field definitions */
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#define DSCSR_CDS BIT(16)
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/* NVIC registers */
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#define NVIC_ICTR 0xE000E004
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#define NVIC_ISE0 0xE000E100
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#define NVIC_ICSR 0xE000ED04
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#define NVIC_AIRCR 0xE000ED0C
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#define NVIC_SHCSR 0xE000ED24
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#define NVIC_CFSR 0xE000ED28
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#define NVIC_MMFSRB 0xE000ED28
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#define NVIC_BFSRB 0xE000ED29
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#define NVIC_USFSRH 0xE000ED2A
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#define NVIC_HFSR 0xE000ED2C
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#define NVIC_DFSR 0xE000ED30
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#define NVIC_MMFAR 0xE000ED34
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#define NVIC_BFAR 0xE000ED38
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#define NVIC_SFSR 0xE000EDE4
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#define NVIC_SFAR 0xE000EDE8
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/* NVIC_AIRCR bits */
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#define AIRCR_VECTKEY (0x5FAul << 16)
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#define AIRCR_SYSRESETREQ BIT(2)
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#define AIRCR_VECTCLRACTIVE BIT(1)
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#define AIRCR_VECTRESET BIT(0)
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/* NVIC_SHCSR bits */
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#define SHCSR_BUSFAULTENA BIT(17)
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/* NVIC_DFSR bits */
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#define DFSR_HALTED 1
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#define DFSR_BKPT 2
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#define DFSR_DWTTRAP 4
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#define DFSR_VCATCH 8
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#define DFSR_EXTERNAL 16
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#define FPCR_CODE 0
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#define FPCR_LITERAL 1
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#define FPCR_REPLACE_REMAP (0ul << 30)
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#define FPCR_REPLACE_BKPT_LOW (1ul << 30)
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#define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
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#define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
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struct cortex_m_fp_comparator {
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bool used;
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int type;
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uint32_t fpcr_value;
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uint32_t fpcr_address;
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};
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struct cortex_m_dwt_comparator {
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bool used;
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uint32_t comp;
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uint32_t mask;
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uint32_t function;
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uint32_t dwt_comparator_address;
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};
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enum cortex_m_soft_reset_config {
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CORTEX_M_RESET_SYSRESETREQ,
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CORTEX_M_RESET_VECTRESET,
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};
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enum cortex_m_isrmasking_mode {
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CORTEX_M_ISRMASK_AUTO,
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CORTEX_M_ISRMASK_OFF,
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CORTEX_M_ISRMASK_ON,
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CORTEX_M_ISRMASK_STEPONLY,
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};
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struct cortex_m_common {
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unsigned int common_magic;
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struct armv7m_common armv7m;
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/* Context information */
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uint32_t dcb_dhcsr;
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uint32_t dcb_dhcsr_cumulated_sticky;
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/* DCB DHCSR has been at least once read, so the sticky bits have been reset */
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bool dcb_dhcsr_sticky_is_recent;
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uint32_t nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
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uint32_t nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
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/* Flash Patch and Breakpoint (FPB) */
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unsigned int fp_num_lit;
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unsigned int fp_num_code;
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int fp_rev;
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bool fpb_enabled;
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struct cortex_m_fp_comparator *fp_comparator_list;
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/* Data Watchpoint and Trace (DWT) */
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unsigned int dwt_num_comp;
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unsigned int dwt_comp_available;
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uint32_t dwt_devarch;
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struct cortex_m_dwt_comparator *dwt_comparator_list;
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struct reg_cache *dwt_cache;
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enum cortex_m_soft_reset_config soft_reset_config;
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bool vectreset_supported;
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enum cortex_m_isrmasking_mode isrmasking_mode;
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const struct cortex_m_part_info *core_info;
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bool slow_register_read; /* A register has not been ready, poll S_REGRDY */
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uint64_t apsel;
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/* Whether this target has the erratum that makes C_MASKINTS not apply to
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* already pending interrupts */
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bool maskints_erratum;
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};
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static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
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{
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return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
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}
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static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common *cortex_m)
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{
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if (!is_cortex_m_or_hla(cortex_m))
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return false;
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return !cortex_m->armv7m.is_hla_target;
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}
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/**
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* @returns the pointer to the target specific struct
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* without matching a magic number.
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* Use in target specific service routines, where the correct
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* type of arch_info is certain.
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*/
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static inline struct cortex_m_common *
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target_to_cm(struct target *target)
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{
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return container_of(target->arch_info,
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struct cortex_m_common, armv7m.arm);
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}
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/**
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* @returns the pointer to the target specific struct
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* or NULL if the magic number does not match.
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* Use in a flash driver or any place where mismatch of the arch_info
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* type can happen.
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*/
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static inline struct cortex_m_common *
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target_to_cortex_m_safe(struct target *target)
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{
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/* Check the parent types first to prevent peeking memory too far
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* from arch_info pointer */
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if (!target_to_armv7m_safe(target))
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return NULL;
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struct cortex_m_common *cortex_m = target_to_cm(target);
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if (!is_cortex_m_or_hla(cortex_m))
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return NULL;
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return cortex_m;
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}
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/**
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* @returns cached value of Cortex-M part number
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* or CORTEX_M_PARTNO_INVALID if the magic number does not match
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* or core_info is not initialised.
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*/
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static inline enum cortex_m_partno cortex_m_get_partno_safe(struct target *target)
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{
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struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
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if (!cortex_m)
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return CORTEX_M_PARTNO_INVALID;
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if (!cortex_m->core_info)
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return CORTEX_M_PARTNO_INVALID;
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return cortex_m->core_info->partno;
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}
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int cortex_m_examine(struct target *target);
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int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
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int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
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int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
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int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
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int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
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int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
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void cortex_m_enable_breakpoints(struct target *target);
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void cortex_m_enable_watchpoints(struct target *target);
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void cortex_m_deinit_target(struct target *target);
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int cortex_m_profiling(struct target *target, uint32_t *samples,
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uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
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#endif /* OPENOCD_TARGET_CORTEX_M_H */
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