372 lines
14 KiB
C
372 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2011 by Rodrigo L. Rosa *
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* rodrigorosa.LG@gmail.com *
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* *
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* Based on dsp563xx_once.h written by Mathias Kuester *
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* mkdorg@users.sourceforge.net *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_DSP5680XX_H
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#define OPENOCD_TARGET_DSP5680XX_H
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#include <jtag/jtag.h>
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/**
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* @file dsp5680xx.h
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* @author Rodrigo Rosa <rodrigorosa.LG@gmail.com>
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* @date Thu Jun 9 18:54:38 2011
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*
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* @brief Basic support for the 5680xx DSP from Freescale.
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* The chip has two taps in the JTAG chain, the Master tap and the Core tap.
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* In this code the Master tap is only used to unlock the flash memory by executing a JTAG instruction.
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*
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*/
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#define S_FILE_DATA_OFFSET 0x200000
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#define TIME_DIV_FREESCALE 0.3
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/** ----------------------------------------------------------------
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* JTAG
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*----------------------------------------------------------------
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*/
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#define DSP5680XX_JTAG_CORE_TAP_IRLEN 4
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#define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8
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#define JTAG_STATUS_MASK 0x0F
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#define JTAG_STATUS_NORMAL 0x01
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#define JTAG_STATUS_STOPWAIT 0x05
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#define JTAG_STATUS_BUSY 0x09
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#define JTAG_STATUS_DEBUG 0x0D
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#define JTAG_STATUS_DEAD 0x0f
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#define JTAG_INSTR_EXTEST 0x0
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#define JTAG_INSTR_SAMPLE_PRELOAD 0x1
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#define JTAG_INSTR_IDCODE 0x2
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#define JTAG_INSTR_EXTEST_PULLUP 0x3
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#define JTAG_INSTR_HIGHZ 0x4
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#define JTAG_INSTR_CLAMP 0x5
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#define JTAG_INSTR_ENABLE_ONCE 0x6
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#define JTAG_INSTR_DEBUG_REQUEST 0x7
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#define JTAG_INSTR_BYPASS 0xF
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/**
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* ----------------------------------------------------------------
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*/
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/** ----------------------------------------------------------------
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* Master TAP instructions from MC56F8000RM.pdf
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* ----------------------------------------------------------------
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*/
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#define MASTER_TAP_CMD_BYPASS 0xF
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#define MASTER_TAP_CMD_IDCODE 0x2
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#define MASTER_TAP_CMD_TLM_SEL 0x5
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#define MASTER_TAP_CMD_FLASH_ERASE 0x8
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/**
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* ----------------------------------------------------------------
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*/
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/** ----------------------------------------------------------------
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* EOnCE control register info
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_OCR_EX (1<<5)
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/* EX Bit Definition
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0 Remain in the Debug Processing State
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1 Leave the Debug Processing State */
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#define DSP5680XX_ONCE_OCR_GO (1<<6)
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/* GO Bit Definition
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0 Inactive—No Action Taken
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1 Execute Controller Instruction */
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#define DSP5680XX_ONCE_OCR_RW (1<<7)
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/** RW Bit Definition
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* 0 Write To the Register Specified by the RS[4:0] Bits
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* 1 ReadFrom the Register Specified by the RS[4:0] Bits
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* ----------------------------------------------------------------
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*/
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/** ----------------------------------------------------------------
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* EOnCE Status Register
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_OSCR_OS1 (1<<5)
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#define DSP5680XX_ONCE_OSCR_OS0 (1<<4)
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/**
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* ----------------------------------------------------------------
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*/
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/** ----------------------------------------------------------------
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* EOnCE Core Status - Describes the operating status of the core controller
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_OSCR_NORMAL_M (0)
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/* 00 - Normal - Controller Core Executing Instructions or in Reset */
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#define DSP5680XX_ONCE_OSCR_STOPWAIT_M (DSP5680XX_ONCE_OSCR_OS0)
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/* 01 - Stop/Wait - Controller Core in Stop or Wait Mode */
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#define DSP5680XX_ONCE_OSCR_BUSY_M (DSP5680XX_ONCE_OSCR_OS1)
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/* 10 - Busy - Controller is Performing External or Peripheral Access (Wait States) */
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#define DSP5680XX_ONCE_OSCR_DEBUG_M (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1)
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/* 11 - Debug - Controller Core Halted and in Debug Mode */
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#define EONCE_STAT_MASK 0x30
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/**
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* ----------------------------------------------------------------
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*/
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/** ----------------------------------------------------------------
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* Register Select Encoding (eonce_rev.1.0_0208081.pdf:14)
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */
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#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */
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#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */
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#define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */
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#define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */
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#define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */
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#define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */
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#define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */
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#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
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#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
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#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
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#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
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#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
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#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
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#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
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#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
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#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
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#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
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#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
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/**
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* ----------------------------------------------------------------
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*/
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#define FLUSH_COUNT_READ_WRITE 8192 /* This value works, higher values (and lower...) may work as well. */
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#define FLUSH_COUNT_FLASH 8192
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/** ----------------------------------------------------------------
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* HFM (flash module) Commands (ref:MC56F801xRM.pdf:159)
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* ----------------------------------------------------------------
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*/
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#define HFM_ERASE_VERIFY 0x05
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#define HFM_CALCULATE_DATA_SIGNATURE 0x06
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#define HFM_WORD_PROGRAM 0x20
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#define HFM_PAGE_ERASE 0x40
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#define HFM_MASS_ERASE 0x41
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#define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66
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/**
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* ----------------------------------------------------------------
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*/
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/** ----------------------------------------------------------------
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* Flashing (ref:MC56F801xRM.pdf:159)
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* ----------------------------------------------------------------
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*/
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#define HFM_BASE_ADDR 0x0F400 /** In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR
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* to get data into x: mem.)
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*/
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/**
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* The following are register addresses, not memory
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* addresses (though all registers are memory mapped)
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*/
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#define HFM_CLK_DIV 0x00 /* r/w */
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#define HFM_CNFG 0x01 /* r/w */
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#define HFM_SECHI 0x03 /* r */
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#define HFM_SECLO 0x04 /* r */
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#define HFM_PROT 0x10 /* r/w */
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#define HFM_PROTB 0x11 /* r/w */
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#define HFM_USTAT 0x13 /* r/w */
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#define HFM_CMD 0x14 /* r/w */
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#define HFM_DATA 0x18 /* r */
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#define HFM_OPT1 0x1B /* r */
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#define HFM_TSTSIG 0x1D /* r */
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#define HFM_EXEC_COMPLETE 0x40
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/* User status register (USTAT) masks (MC56F80XXRM.pdf:6.7.5) */
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#define HFM_USTAT_MASK_BLANK 0x4
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#define HFM_USTAT_MASK_PVIOL_ACCER 0x30
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/**
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* The value used on for the FM clock is important to prevent flashing errors and to prevent deterioration of the FM.
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* This value was calculated using a spreadsheet tool available on the Freescale website under FAQ 25464.
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*
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*/
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#define HFM_CLK_DEFAULT 0x27
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/* 0x27 according to freescale cfg, but 0x40 according to freescale spreadsheet... */
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#define HFM_FLASH_BASE_ADDR 0x0
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#define HFM_SIZE_BYTES 0x4000 /* bytes */
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#define HFM_SIZE_WORDS 0x2000 /* words */
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#define HFM_SECTOR_SIZE 0x200 /* Size in bytes */
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#define HFM_SECTOR_COUNT 0x20
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/* A 16K block in pages of 256 words. */
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/**
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* Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset.
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*/
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#define HFM_LOCK_FLASH 0xE70A
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#define HFM_LOCK_ADDR_L 0x1FF7
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#define HFM_LOCK_ADDR_H 0x1FF8
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/**
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* ----------------------------------------------------------------
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*/
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/** ----------------------------------------------------------------
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* Register Memory Map (eonce_rev.1.0_0208081.pdf:16)
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* ----------------------------------------------------------------
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*/
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#define MC568013_EONCE_OBASE_ADDR 0xFF
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/* The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...) */
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#define MC568013_EONCE_TX_RX_ADDR 0xFFFE
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#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF /* Relative to EONCE_OBASE_ADDR */
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#define MC568013_EONCE_OCR 0xFFA0 /* Relative to EONCE_OBASE_ADDR */
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/**
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* ----------------------------------------------------------------
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*/
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/** ----------------------------------------------------------------
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* SIM addresses & commands (MC56F80xx.h from freescale)
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* ----------------------------------------------------------------
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*/
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#define MC568013_SIM_BASE_ADDR 0xF140
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#define MC56803X_2X_SIM_BASE_ADDR 0xF100
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#define SIM_CMD_RESET 0x10
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/**
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* ----------------------------------------------------------------
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*/
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/**
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* ----------------------------------------------------------------
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* ERROR codes - enable automatic parsing of output
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ERROR_UNKNOWN_OR_ERROR_OPENOCD -100
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#define DSP5680XX_ERROR_JTAG_COMM -1
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#define DSP5680XX_ERROR_JTAG_RESET -2
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#define DSP5680XX_ERROR_JTAG_INVALID_TAP -3
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#define DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW -4
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#define DSP5680XX_ERROR_INVALID_IR_LEN -5
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#define DSP5680XX_ERROR_JTAG_TAP_ENABLE_MASTER -6
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#define DSP5680XX_ERROR_JTAG_TAP_ENABLE_CORE -7
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#define DSP5680XX_ERROR_JTAG_TAP_FIND_MASTER -8
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#define DSP5680XX_ERROR_JTAG_TAP_FIND_CORE -9
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#define DSP5680XX_ERROR_JTAG_DRSCAN -10
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#define DSP5680XX_ERROR_JTAG_IRSCAN -11
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#define DSP5680XX_ERROR_ENTER_DEBUG_MODE -12
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#define DSP5680XX_ERROR_RESUME -13
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#define DSP5680XX_ERROR_WRITE_WITH_TARGET_RUNNING -14
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#define DSP5680XX_ERROR_INVALID_DATA_SIZE_UNIT -15
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#define DSP5680XX_ERROR_PROTECT_CHECK_INVALID_ARGS -16
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#define DSP5680XX_ERROR_FM_BUSY -17
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#define DSP5680XX_ERROR_FM_CMD_TIMED_OUT -18
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#define DSP5680XX_ERROR_FM_EXEC -19
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#define DSP5680XX_ERROR_FM_SET_CLK -20
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#define DSP5680XX_ERROR_FLASHING_INVALID_WORD_COUNT -21
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#define DSP5680XX_ERROR_FLASHING_CRC -22
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#define DSP5680XX_ERROR_FLASHING -23
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#define DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP -24
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#define DSP5680XX_ERROR_HALT -25
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#define DSP5680XX_ERROR_EXIT_DEBUG_MODE -26
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#define DSP5680XX_ERROR_TARGET_RUNNING -27
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#define DSP5680XX_ERROR_NOT_IN_DEBUG -28
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/**
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* ----------------------------------------------------------------
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*/
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struct dsp5680xx_common {
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uint32_t stored_pc;
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int flush;
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bool debug_mode_enabled;
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};
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extern struct dsp5680xx_common dsp5680xx_context;
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static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target
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*target)
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{
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return target->arch_info;
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}
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/**
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* Writes to flash memory.
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* Does not check if flash is erased, it's up to the user to erase the flash before running
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* this function.
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* The flashing algorithm runs from RAM, reading from a register to which this function
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* writes to. The algorithm is open loop, there is no control to verify that the FM read
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* the register before writing the next data. A closed loop approach was much slower,
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* and the current implementation does not fail, and if it did the crc check would detect it,
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* allowing to flash again.
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*
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* @param target
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* @param buffer
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* @param address Word addressing.
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* @param count In bytes.
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* @param is_flash_lock
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*
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* @return
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*/
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int dsp5680xx_f_wr(struct target *target, const uint8_t *buffer, uint32_t address,
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uint32_t count, int is_flash_lock);
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/**
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* The FM has the functionality of checking if the flash array is erased. This function
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* executes it. It does not support individual sector analysis.
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*
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* @param target
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* @param erased
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* @param sector This parameter is ignored because the FM does not support checking if
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* individual sectors are erased.
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*
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* @return
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*/
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int dsp5680xx_f_erase_check(struct target *target, uint8_t *erased,
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uint32_t sector);
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/**
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* Erases either a sector or the complete flash array. If either the range first-last covers
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* the complete array or if first == 0 and last == 0 then a mass erase command is executed
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* on the FM. If not, then individual sectors are erased.
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*
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* @param target
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* @param first
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* @param last
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*
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* @return
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*/
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int dsp5680xx_f_erase(struct target *target, int first, int last);
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/**
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* Reads the memory mapped protection register. A 1 implies the sector is protected,
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* a 0 implies the sector is not protected.
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*
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* @param target
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* @param protected Data read from the protection register.
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*
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* @return
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*/
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int dsp5680xx_f_protect_check(struct target *target, uint16_t *protected);
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/**
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* Writes the flash security words with a specific value. The chip's security will be
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* enabled after the first reset following the execution of this function.
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*
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* @param target
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*
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* @return
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*/
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int dsp5680xx_f_lock(struct target *target);
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/**
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* Executes a mass erase command. The must be done from the Master tap.
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* It is up to the user to select the master tap (jtag tapenable dsp5680xx.chp)
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* before running this function.
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* The flash array will be unsecured (and erased) after the first reset following
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* the execution of this function.
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*
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* @param target
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*
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* @return
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*/
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int dsp5680xx_f_unlock(struct target *target);
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#endif /* OPENOCD_TARGET_DSP5680XX_H */
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