424 lines
19 KiB
C
424 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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* *
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* Copyright (C) 2011 by Drasko DRASKOVIC *
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* drasko.draskovic@gmail.com *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_MIPS32_H
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#define OPENOCD_TARGET_MIPS32_H
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#include "target.h"
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#include "mips32_pracc.h"
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#define MIPS32_COMMON_MAGIC 0xB320B320U
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/**
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* Memory segments (32bit kernel mode addresses)
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* These are the traditional names used in the 32-bit universe.
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*/
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#define KUSEG 0x00000000
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#define KSEG0 0x80000000
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#define KSEG1 0xa0000000
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#define KSEG2 0xc0000000
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#define KSEG3 0xe0000000
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/** Returns the kernel segment base of a given address */
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#define KSEGX(a) ((a) & 0xe0000000)
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/** CP0 CONFIG register fields */
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#define MIPS32_CONFIG0_KU_SHIFT 25
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#define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)
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#define MIPS32_CONFIG0_K0_SHIFT 0
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#define MIPS32_CONFIG0_K0_MASK (0x7 << MIPS32_CONFIG0_K0_SHIFT)
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#define MIPS32_CONFIG0_K23_SHIFT 28
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#define MIPS32_CONFIG0_K23_MASK (0x7 << MIPS32_CONFIG0_K23_SHIFT)
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#define MIPS32_CONFIG0_AR_SHIFT 10
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#define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)
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#define MIPS32_CONFIG1_DL_SHIFT 10
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#define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)
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#define MIPS32_CONFIG3_ISA_SHIFT 14
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#define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT)
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#define MIPS32_ARCH_REL1 0x0
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#define MIPS32_ARCH_REL2 0x1
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#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
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/* offsets into mips32 core register cache */
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enum {
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MIPS32_PC = 37,
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MIPS32_FIR = 71,
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MIPS32NUMCOREREGS
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};
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enum mips32_isa_mode {
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MIPS32_ISA_MIPS32 = 0,
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MIPS32_ISA_MIPS16E = 1,
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MIPS32_ISA_MMIPS32 = 3,
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};
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enum mips32_isa_imp {
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MIPS32_ONLY = 0,
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MMIPS32_ONLY = 1,
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MIPS32_MIPS16 = 2,
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MIPS32_MMIPS32 = 3,
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};
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struct mips32_comparator {
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int used;
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uint32_t bp_value;
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uint32_t reg_address;
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};
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struct mips32_common {
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unsigned int common_magic;
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void *arch_info;
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struct reg_cache *core_cache;
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struct mips_ejtag ejtag_info;
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uint32_t core_regs[MIPS32NUMCOREREGS];
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enum mips32_isa_mode isa_mode;
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enum mips32_isa_imp isa_imp;
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/* working area for fastdata access */
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struct working_area *fast_data_area;
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int bp_scanned;
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int num_inst_bpoints;
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int num_data_bpoints;
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int num_inst_bpoints_avail;
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int num_data_bpoints_avail;
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struct mips32_comparator *inst_break_list;
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struct mips32_comparator *data_break_list;
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target *target, unsigned int num);
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int (*write_core_reg)(struct target *target, unsigned int num);
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};
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static inline struct mips32_common *
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target_to_mips32(struct target *target)
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{
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return target->arch_info;
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}
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struct mips32_core_reg {
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uint32_t num;
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struct target *target;
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struct mips32_common *mips32_common;
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};
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struct mips32_algorithm {
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unsigned int common_magic;
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enum mips32_isa_mode isa_mode;
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};
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#define MIPS32_OP_ADDU 0x21u
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#define MIPS32_OP_ADDIU 0x09u
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#define MIPS32_OP_ANDI 0x0Cu
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#define MIPS32_OP_BEQ 0x04u
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#define MIPS32_OP_BGTZ 0x07u
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#define MIPS32_OP_BNE 0x05u
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#define MIPS32_OP_ADDI 0x08u
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#define MIPS32_OP_AND 0x24u
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#define MIPS32_OP_CACHE 0x2Fu
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#define MIPS32_OP_COP0 0x10u
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#define MIPS32_OP_J 0x02u
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#define MIPS32_OP_JR 0x08u
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#define MIPS32_OP_LUI 0x0Fu
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#define MIPS32_OP_LW 0x23u
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#define MIPS32_OP_LB 0x20u
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#define MIPS32_OP_LBU 0x24u
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#define MIPS32_OP_LHU 0x25u
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#define MIPS32_OP_MFHI 0x10u
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#define MIPS32_OP_MTHI 0x11u
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#define MIPS32_OP_MFLO 0x12u
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#define MIPS32_OP_MTLO 0x13u
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#define MIPS32_OP_RDHWR 0x3Bu
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#define MIPS32_OP_SB 0x28u
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#define MIPS32_OP_SH 0x29u
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#define MIPS32_OP_SW 0x2Bu
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#define MIPS32_OP_ORI 0x0Du
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#define MIPS32_OP_XORI 0x0Eu
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#define MIPS32_OP_XOR 0x26u
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#define MIPS32_OP_SLTU 0x2Bu
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#define MIPS32_OP_SRL 0x03u
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#define MIPS32_OP_SYNCI 0x1Fu
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#define MIPS32_OP_SLL 0x00u
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#define MIPS32_OP_SLTI 0x0Au
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#define MIPS32_OP_MOVN 0x0Bu
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#define MIPS32_OP_REGIMM 0x01u
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#define MIPS32_OP_SDBBP 0x3Fu
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#define MIPS32_OP_SPECIAL 0x00u
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#define MIPS32_OP_SPECIAL2 0x07u
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#define MIPS32_OP_SPECIAL3 0x1Fu
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#define MIPS32_COP0_MF 0x00u
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#define MIPS32_COP0_MT 0x04u
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#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \
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(((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
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#define MIPS32_I_INST(opcode, rs, rt, immd) \
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(((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd))
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#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr))
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#define MIPS32_ISA_NOP 0
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#define MIPS32_ISA_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
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#define MIPS32_ISA_ADDIU(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val)
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#define MIPS32_ISA_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU)
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#define MIPS32_ISA_AND(dst, src, tar) MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND)
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#define MIPS32_ISA_ANDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val)
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#define MIPS32_ISA_B(off) MIPS32_ISA_BEQ(0, 0, off)
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#define MIPS32_ISA_BEQ(src, tar, off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
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#define MIPS32_ISA_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
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#define MIPS32_ISA_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
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#define MIPS32_ISA_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
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#define MIPS32_ISA_J(tar) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)
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#define MIPS32_ISA_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
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#define MIPS32_ISA_LB(reg, off, base) MIPS32_I_INST(MIPS32_OP_LB, base, reg, off)
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#define MIPS32_ISA_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
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#define MIPS32_ISA_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
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#define MIPS32_ISA_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
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#define MIPS32_ISA_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
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#define MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
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#define MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
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#define MIPS32_ISA_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
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#define MIPS32_ISA_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
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#define MIPS32_ISA_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
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#define MIPS32_ISA_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
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#define MIPS32_ISA_MOVN(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN)
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#define MIPS32_ISA_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
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#define MIPS32_ISA_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
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#define MIPS32_ISA_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
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#define MIPS32_ISA_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
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#define MIPS32_ISA_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
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#define MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)
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#define MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)
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#define MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
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#define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL)
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#define MIPS32_ISA_SYNC 0xFu
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#define MIPS32_ISA_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)
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#define MIPS32_ISA_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)
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#define MIPS32_ISA_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)
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#define MIPS32_ISA_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */
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/**
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* Cache operations definitions
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* Operation field is 5 bits long :
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* 1) bits 1..0 hold cache type
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* 2) bits 4..2 hold operation code
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*/
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#define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2))
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#define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2))
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/* ejtag specific instructions */
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#define MIPS32_ISA_DRET 0x4200001Fu
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/* MIPS32_ISA_J_INST(MIPS32_ISA_OP_SPECIAL2, MIPS32_ISA_OP_SDBBP) */
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#define MIPS32_ISA_SDBBP 0x7000003Fu
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#define MIPS16_ISA_SDBBP 0xE801u
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/*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
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#define POOL32A 0X00u
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#define POOL32AXF 0x3Cu
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#define POOL32B 0x08u
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#define POOL32I 0x10u
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#define MMIPS32_OP_ADDI 0x04u
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#define MMIPS32_OP_ADDIU 0x0Cu
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#define MMIPS32_OP_ADDU 0x150u
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#define MMIPS32_OP_AND 0x250u
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#define MMIPS32_OP_ANDI 0x34u
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#define MMIPS32_OP_BEQ 0x25u
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#define MMIPS32_OP_BGTZ 0x06u
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#define MMIPS32_OP_BNE 0x2Du
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#define MMIPS32_OP_CACHE 0x06u
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#define MMIPS32_OP_J 0x35u
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#define MMIPS32_OP_JALR 0x03Cu
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#define MMIPS32_OP_LB 0x07u
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#define MMIPS32_OP_LBU 0x05u
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#define MMIPS32_OP_LHU 0x0Du
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#define MMIPS32_OP_LUI 0x0Du
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#define MMIPS32_OP_LW 0x3Fu
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#define MMIPS32_OP_MFC0 0x03u
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#define MMIPS32_OP_MTC0 0x0Bu
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#define MMIPS32_OP_MFLO 0x075u
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#define MMIPS32_OP_MFHI 0x035u
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#define MMIPS32_OP_MTLO 0x0F5u
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#define MMIPS32_OP_MTHI 0x0B5u
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#define MMIPS32_OP_MOVN 0x018u
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#define MMIPS32_OP_ORI 0x14u
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#define MMIPS32_OP_RDHWR 0x1ACu
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#define MMIPS32_OP_SB 0x06u
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#define MMIPS32_OP_SH 0x0Eu
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#define MMIPS32_OP_SW 0x3Eu
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#define MMIPS32_OP_SLTU 0x390u
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#define MMIPS32_OP_SLL 0x000u
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#define MMIPS32_OP_SLTI 0x24u
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#define MMIPS32_OP_SRL 0x040u
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#define MMIPS32_OP_SYNCI 0x10u
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#define MMIPS32_OP_XOR 0x310u
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#define MMIPS32_OP_XORI 0x1Cu
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#define MMIPS32_ADDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)
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#define MMIPS32_ADDIU(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)
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#define MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)
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#define MMIPS32_AND(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)
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#define MMIPS32_ANDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)
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#define MMIPS32_B(off) MMIPS32_BEQ(0, 0, off)
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#define MMIPS32_BEQ(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)
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#define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(POOL32I, MMIPS32_OP_BGTZ, reg, off)
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#define MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)
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#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
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#define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
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#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF)
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#define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
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#define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
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#define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
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#define MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val)
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#define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
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#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF)
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#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF)
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#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF)
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#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF)
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#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF)
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#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF)
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#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
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#define MMIPS32_NOP 0
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#define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
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#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF)
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#define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
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#define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
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#define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
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#define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
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#define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
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#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off)
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#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
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#define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
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#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */
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#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
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#define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
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#define MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */
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/* ejtag specific instructions */
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#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */
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#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */
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#define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */
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/* instruction code with isa selection */
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#define MIPS32_NOP 0 /* same for both isa's */
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#define MIPS32_ADDI(isa, tar, src, val) (isa ? MMIPS32_ADDI(tar, src, val) : MIPS32_ISA_ADDI(tar, src, val))
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#define MIPS32_ADDIU(isa, tar, src, val) (isa ? MMIPS32_ADDIU(tar, src, val) : MIPS32_ISA_ADDIU(tar, src, val))
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#define MIPS32_ADDU(isa, dst, src, tar) (isa ? MMIPS32_ADDU(dst, src, tar) : MIPS32_ISA_ADDU(dst, src, tar))
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#define MIPS32_AND(isa, dst, src, tar) (isa ? MMIPS32_AND(dst, src, tar) : MIPS32_ISA_AND(dst, src, tar))
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#define MIPS32_ANDI(isa, tar, src, val) (isa ? MMIPS32_ANDI(tar, src, val) : MIPS32_ISA_ANDI(tar, src, val))
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#define MIPS32_B(isa, off) (isa ? MMIPS32_B(off) : MIPS32_ISA_B(off))
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#define MIPS32_BEQ(isa, src, tar, off) (isa ? MMIPS32_BEQ(src, tar, off) : MIPS32_ISA_BEQ(src, tar, off))
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#define MIPS32_BGTZ(isa, reg, off) (isa ? MMIPS32_BGTZ(reg, off) : MIPS32_ISA_BGTZ(reg, off))
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#define MIPS32_BNE(isa, src, tar, off) (isa ? MMIPS32_BNE(src, tar, off) : MIPS32_ISA_BNE(src, tar, off))
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#define MIPS32_CACHE(isa, op, off, base) (isa ? MMIPS32_CACHE(op, off, base) : MIPS32_ISA_CACHE(op, off, base))
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#define MIPS32_J(isa, tar) (isa ? MMIPS32_J(tar) : MIPS32_ISA_J(tar))
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#define MIPS32_JR(isa, reg) (isa ? MMIPS32_JR(reg) : MIPS32_ISA_JR(reg))
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#define MIPS32_LB(isa, reg, off, base) (isa ? MMIPS32_LB(reg, off, base) : MIPS32_ISA_LB(reg, off, base))
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#define MIPS32_LBU(isa, reg, off, base) (isa ? MMIPS32_LBU(reg, off, base) : MIPS32_ISA_LBU(reg, off, base))
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#define MIPS32_LHU(isa, reg, off, base) (isa ? MMIPS32_LHU(reg, off, base) : MIPS32_ISA_LHU(reg, off, base))
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#define MIPS32_LW(isa, reg, off, base) (isa ? MMIPS32_LW(reg, off, base) : MIPS32_ISA_LW(reg, off, base))
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#define MIPS32_LUI(isa, reg, val) (isa ? MMIPS32_LUI(reg, val) : MIPS32_ISA_LUI(reg, val))
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#define MIPS32_MFC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MFC0(gpr, cpr, sel) : MIPS32_ISA_MFC0(gpr, cpr, sel))
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#define MIPS32_MTC0(isa, gpr, cpr, sel) (isa ? MMIPS32_MTC0(gpr, cpr, sel) : MIPS32_ISA_MTC0(gpr, cpr, sel))
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#define MIPS32_MFLO(isa, reg) (isa ? MMIPS32_MFLO(reg) : MIPS32_ISA_MFLO(reg))
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#define MIPS32_MFHI(isa, reg) (isa ? MMIPS32_MFHI(reg) : MIPS32_ISA_MFHI(reg))
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#define MIPS32_MTLO(isa, reg) (isa ? MMIPS32_MTLO(reg) : MIPS32_ISA_MTLO(reg))
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#define MIPS32_MTHI(isa, reg) (isa ? MMIPS32_MTHI(reg) : MIPS32_ISA_MTHI(reg))
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#define MIPS32_MOVN(isa, dst, src, tar) (isa ? MMIPS32_MOVN(dst, src, tar) : MIPS32_ISA_MOVN(dst, src, tar))
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#define MIPS32_ORI(isa, tar, src, val) (isa ? MMIPS32_ORI(tar, src, val) : MIPS32_ISA_ORI(tar, src, val))
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#define MIPS32_RDHWR(isa, tar, dst) (isa ? MMIPS32_RDHWR(tar, dst) : MIPS32_ISA_RDHWR(tar, dst))
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#define MIPS32_SB(isa, reg, off, base) (isa ? MMIPS32_SB(reg, off, base) : MIPS32_ISA_SB(reg, off, base))
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#define MIPS32_SH(isa, reg, off, base) (isa ? MMIPS32_SH(reg, off, base) : MIPS32_ISA_SH(reg, off, base))
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#define MIPS32_SW(isa, reg, off, base) (isa ? MMIPS32_SW(reg, off, base) : MIPS32_ISA_SW(reg, off, base))
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#define MIPS32_SLL(isa, dst, src, sa) (isa ? MMIPS32_SLL(dst, src, sa) : MIPS32_ISA_SLL(dst, src, sa))
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#define MIPS32_SLTI(isa, tar, src, val) (isa ? MMIPS32_SLTI(tar, src, val) : MIPS32_ISA_SLTI(tar, src, val))
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#define MIPS32_SLTU(isa, dst, src, tar) (isa ? MMIPS32_SLTU(dst, src, tar) : MIPS32_ISA_SLTU(dst, src, tar))
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#define MIPS32_SRL(isa, reg, src, off) (isa ? MMIPS32_SRL(reg, src, off) : MIPS32_ISA_SRL(reg, src, off))
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#define MIPS32_SYNCI(isa, off, base) (isa ? MMIPS32_SYNCI(off, base) : MIPS32_ISA_SYNCI(off, base))
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#define MIPS32_SYNC(isa) (isa ? MMIPS32_SYNC : MIPS32_ISA_SYNC)
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#define MIPS32_XOR(isa, reg, val1, val2) (isa ? MMIPS32_XOR(reg, val1, val2) : MIPS32_ISA_XOR(reg, val1, val2))
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#define MIPS32_XORI(isa, tar, src, val) (isa ? MMIPS32_XORI(tar, src, val) : MIPS32_ISA_XORI(tar, src, val))
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#define MIPS32_SYNCI_STEP 0x1
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/* ejtag specific instructions */
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#define MIPS32_DRET(isa) (isa ? MMIPS32_DRET : MIPS32_ISA_DRET)
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#define MIPS32_SDBBP(isa) (isa ? MMIPS32_SDBBP : MIPS32_ISA_SDBBP)
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#define MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)
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extern const struct command_registration mips32_command_handlers[];
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int mips32_arch_state(struct target *target);
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int mips32_init_arch_info(struct target *target,
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struct mips32_common *mips32, struct jtag_tap *tap);
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int mips32_restore_context(struct target *target);
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int mips32_save_context(struct target *target);
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struct reg_cache *mips32_build_reg_cache(struct target *target);
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int mips32_run_algorithm(struct target *target,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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int timeout_ms, void *arch_info);
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int mips32_configure_break_unit(struct target *target);
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int mips32_enable_interrupts(struct target *target, int enable);
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int mips32_examine(struct target *target);
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int mips32_read_config_regs(struct target *target);
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int mips32_register_commands(struct command_context *cmd_ctx);
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int mips32_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size,
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enum target_register_class reg_class);
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int mips32_checksum_memory(struct target *target, target_addr_t address,
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uint32_t count, uint32_t *checksum);
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int mips32_blank_check_memory(struct target *target,
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struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
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#endif /* OPENOCD_TARGET_MIPS32_H */
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