452 lines
13 KiB
C
452 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2008 by John McCarthy *
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* jgmcc@magma.ca *
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* *
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* Copyright (C) 2008 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2008 by David T.L. Wong *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "mips32_dmaacc.h"
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#include <helper/time_support.h>
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static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info,
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uint32_t addr, int count, uint8_t *buf);
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static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info,
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uint32_t addr, int count, uint16_t *buf);
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static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info,
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uint32_t addr, int count, uint32_t *buf);
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static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info,
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uint32_t addr, int count, const uint8_t *buf);
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static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info,
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uint32_t addr, int count, const uint16_t *buf);
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static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info,
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uint32_t addr, int count, const uint32_t *buf);
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/*
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* The following logic shamelessly cloned from HairyDairyMaid's wrt54g_debrick
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* to support the Broadcom BCM5352 SoC in the Linksys WRT54GL wireless router
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* (and any others that support EJTAG DMA transfers).
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* Note: This only supports memory read/write. Since the BCM5352 doesn't
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* appear to support PRACC accesses, all debug functions except halt
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* do not work. Still, this does allow erasing/writing flash as well as
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* displaying/modifying memory and memory mapped registers.
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*/
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static int ejtag_dma_dstrt_poll(struct mips_ejtag *ejtag_info)
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{
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uint32_t ejtag_ctrl;
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int64_t start = timeval_ms();
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do {
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if (timeval_ms() - start > 1000) {
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LOG_ERROR("DMA time out");
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return -ETIMEDOUT;
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}
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ejtag_ctrl = EJTAG_CTRL_DMAACC | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
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return 0;
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}
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static int ejtag_dma_read(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t *data)
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{
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uint32_t v;
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uint32_t ejtag_ctrl;
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int retries = RETRY_ATTEMPTS;
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begin_ejtag_dma_read:
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Initiate DMA Read & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* Wait for DSTRT to Clear */
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ejtag_dma_dstrt_poll(ejtag_info);
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/* Read Data */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
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mips_ejtag_drscan_32(ejtag_info, data);
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR) {
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if (retries--) {
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LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
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goto begin_ejtag_dma_read;
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} else
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LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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static int ejtag_dma_read_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint16_t *data)
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{
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uint32_t v;
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uint32_t ejtag_ctrl;
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int retries = RETRY_ATTEMPTS;
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begin_ejtag_dma_read_h:
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Initiate DMA Read & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD |
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EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* Wait for DSTRT to Clear */
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ejtag_dma_dstrt_poll(ejtag_info);
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/* Read Data */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR) {
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if (retries--) {
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LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
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goto begin_ejtag_dma_read_h;
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} else
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LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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/* Handle the bigendian/littleendian */
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if (addr & 0x2)
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*data = (v >> 16) & 0xffff;
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else
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*data = (v & 0x0000ffff);
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return ERROR_OK;
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}
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static int ejtag_dma_read_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint8_t *data)
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{
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uint32_t v;
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uint32_t ejtag_ctrl;
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int retries = RETRY_ATTEMPTS;
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begin_ejtag_dma_read_b:
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Initiate DMA Read & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* Wait for DSTRT to Clear */
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ejtag_dma_dstrt_poll(ejtag_info);
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/* Read Data */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR) {
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if (retries--) {
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LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ (retrying)", addr);
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goto begin_ejtag_dma_read_b;
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} else
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LOG_ERROR("DMA Read Addr = %08" PRIx32 " Data = ERROR ON READ", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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/* Handle the bigendian/littleendian */
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switch (addr & 0x3) {
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case 0:
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*data = v & 0xff;
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break;
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case 1:
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*data = (v >> 8) & 0xff;
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break;
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case 2:
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*data = (v >> 16) & 0xff;
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break;
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case 3:
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*data = (v >> 24) & 0xff;
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break;
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}
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return ERROR_OK;
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}
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static int ejtag_dma_write(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
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{
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uint32_t v;
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uint32_t ejtag_ctrl;
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int retries = RETRY_ATTEMPTS;
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begin_ejtag_dma_write:
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Setup Data */
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Initiate DMA Write & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* Wait for DSTRT to Clear */
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ejtag_dma_dstrt_poll(ejtag_info);
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR) {
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if (retries--) {
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LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
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goto begin_ejtag_dma_write;
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} else
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LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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static int ejtag_dma_write_h(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
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{
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uint32_t v;
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uint32_t ejtag_ctrl;
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int retries = RETRY_ATTEMPTS;
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/* Handle the bigendian/littleendian */
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data &= 0xffff;
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data |= data << 16;
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begin_ejtag_dma_write_h:
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/* Setup Address */
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Setup Data */
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Initiate DMA Write & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* Wait for DSTRT to Clear */
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ejtag_dma_dstrt_poll(ejtag_info);
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR) {
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if (retries--) {
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LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
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goto begin_ejtag_dma_write_h;
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} else
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LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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static int ejtag_dma_write_b(struct mips_ejtag *ejtag_info, uint32_t addr, uint32_t data)
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{
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uint32_t v;
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uint32_t ejtag_ctrl;
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int retries = RETRY_ATTEMPTS;
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/* Handle the bigendian/littleendian */
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data &= 0xff;
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data |= data << 8;
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data |= data << 16;
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begin_ejtag_dma_write_b:
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/* Setup Address*/
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v = addr;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Setup Data */
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v = data;
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
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mips_ejtag_drscan_32(ejtag_info, &v);
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/* Initiate DMA Write & set DSTRT */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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/* Wait for DSTRT to Clear */
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ejtag_dma_dstrt_poll(ejtag_info);
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/* Clear DMA & Check DERR */
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mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
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ejtag_ctrl = ejtag_info->ejtag_ctrl;
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mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
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if (ejtag_ctrl & EJTAG_CTRL_DERR) {
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if (retries--) {
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LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE (retrying)", addr);
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goto begin_ejtag_dma_write_b;
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} else
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LOG_ERROR("DMA Write Addr = %08" PRIx32 " Data = ERROR ON WRITE", addr);
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return ERROR_JTAG_DEVICE_ERROR;
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}
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return ERROR_OK;
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}
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int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf)
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{
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switch (size) {
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case 1:
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return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf);
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case 2:
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return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf);
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case 4:
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return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf);
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}
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return ERROR_OK;
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}
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static int mips32_dmaacc_read_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint32_t *buf)
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{
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int i;
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int retval;
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for (i = 0; i < count; i++) {
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retval = ejtag_dma_read(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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static int mips32_dmaacc_read_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint16_t *buf)
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{
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int i;
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int retval;
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for (i = 0; i < count; i++) {
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retval = ejtag_dma_read_h(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, uint8_t *buf)
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{
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int i;
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int retval;
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for (i = 0; i < count; i++) {
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retval = ejtag_dma_read_b(ejtag_info, addr + i * sizeof(*buf), &buf[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf)
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{
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switch (size) {
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case 1:
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return mips32_dmaacc_write_mem8(ejtag_info, addr, count, buf);
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case 2:
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return mips32_dmaacc_write_mem16(ejtag_info, addr, count, buf);
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case 4:
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return mips32_dmaacc_write_mem32(ejtag_info, addr, count, buf);
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}
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return ERROR_OK;
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}
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static int mips32_dmaacc_write_mem32(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint32_t *buf)
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{
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int i;
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int retval;
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for (i = 0; i < count; i++) {
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retval = ejtag_dma_write(ejtag_info, addr + i * sizeof(*buf), buf[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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static int mips32_dmaacc_write_mem16(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint16_t *buf)
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{
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int i;
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int retval;
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for (i = 0; i < count; i++) {
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retval = ejtag_dma_write_h(ejtag_info, addr + i * sizeof(*buf), buf[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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static int mips32_dmaacc_write_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int count, const uint8_t *buf)
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{
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int i;
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int retval;
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for (i = 0; i < count; i++) {
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retval = ejtag_dma_write_b(ejtag_info, addr + i * sizeof(*buf), buf[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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