1124 lines
28 KiB
C
1124 lines
28 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2013 Andes Technology *
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* Hsiangkai Wang <hkwang@andestech.com> *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/command.h>
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#include "nds32.h"
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#include "nds32_aice.h"
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#include "nds32_disassembler.h"
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extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM];
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extern uint32_t nds32_edm_ops_num;
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static const char *const nds_memory_access_name[] = {
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"BUS",
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"CPU",
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};
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static const char *const nds_memory_select_name[] = {
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"AUTO",
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"MEM",
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"ILM",
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"DLM",
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};
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COMMAND_HANDLER(handle_nds32_dssim_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (strcmp(CMD_ARGV[0], "on") == 0)
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nds32->step_isr_enable = true;
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if (strcmp(CMD_ARGV[0], "off") == 0)
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nds32->step_isr_enable = false;
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}
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command_print(CMD, "%s: $INT_MASK.DSSIM: %d", target_name(target),
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nds32->step_isr_enable);
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_memory_access_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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struct aice_port_s *aice = target_to_aice(target);
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struct nds32_memory *memory = &(nds32->memory);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (strcmp(CMD_ARGV[0], "bus") == 0)
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memory->access_channel = NDS_MEMORY_ACC_BUS;
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else if (strcmp(CMD_ARGV[0], "cpu") == 0)
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memory->access_channel = NDS_MEMORY_ACC_CPU;
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else /* default access channel is NDS_MEMORY_ACC_CPU */
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memory->access_channel = NDS_MEMORY_ACC_CPU;
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LOG_DEBUG("memory access channel is changed to %s",
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nds_memory_access_name[memory->access_channel]);
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aice_memory_access(aice, memory->access_channel);
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} else {
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command_print(CMD, "%s: memory access channel: %s",
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target_name(target),
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nds_memory_access_name[memory->access_channel]);
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}
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_memory_mode_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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struct aice_port_s *aice = target_to_aice(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (nds32->edm.access_control == false) {
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command_print(CMD, "%s does not support ACC_CTL. "
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"Set memory mode to MEMORY", target_name(target));
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nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
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} else if (nds32->edm.direct_access_local_memory == false) {
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command_print(CMD, "%s does not support direct access "
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"local memory. Set memory mode to MEMORY",
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target_name(target));
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nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
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/* set to ACC_CTL */
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aice_memory_mode(aice, nds32->memory.mode);
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} else {
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if (strcmp(CMD_ARGV[0], "auto") == 0) {
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nds32->memory.mode = NDS_MEMORY_SELECT_AUTO;
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} else if (strcmp(CMD_ARGV[0], "mem") == 0) {
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nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
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} else if (strcmp(CMD_ARGV[0], "ilm") == 0) {
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if (nds32->memory.ilm_base == 0)
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command_print(CMD, "%s does not support ILM",
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target_name(target));
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else
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nds32->memory.mode = NDS_MEMORY_SELECT_ILM;
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} else if (strcmp(CMD_ARGV[0], "dlm") == 0) {
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if (nds32->memory.dlm_base == 0)
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command_print(CMD, "%s does not support DLM",
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target_name(target));
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else
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nds32->memory.mode = NDS_MEMORY_SELECT_DLM;
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}
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/* set to ACC_CTL */
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aice_memory_mode(aice, nds32->memory.mode);
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}
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}
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command_print(CMD, "%s: memory mode: %s",
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target_name(target),
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nds_memory_select_name[nds32->memory.mode]);
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_cache_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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struct aice_port_s *aice = target_to_aice(target);
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struct nds32_cache *icache = &(nds32->memory.icache);
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struct nds32_cache *dcache = &(nds32->memory.dcache);
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int result;
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
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if ((dcache->line_size != 0) && (dcache->enable == true)) {
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/* D$ write back */
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result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
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if (result != ERROR_OK) {
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command_print(CMD, "%s: Write back data cache...failed",
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target_name(target));
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return result;
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}
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command_print(CMD, "%s: Write back data cache...done",
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target_name(target));
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/* D$ invalidate */
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result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
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if (result != ERROR_OK) {
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command_print(CMD, "%s: Invalidate data cache...failed",
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target_name(target));
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return result;
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}
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command_print(CMD, "%s: Invalidate data cache...done",
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target_name(target));
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} else {
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if (dcache->line_size == 0)
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command_print(CMD, "%s: No data cache",
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target_name(target));
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else
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command_print(CMD, "%s: Data cache disabled",
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target_name(target));
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}
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if ((icache->line_size != 0) && (icache->enable == true)) {
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/* I$ invalidate */
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result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
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if (result != ERROR_OK) {
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command_print(CMD, "%s: Invalidate instruction cache...failed",
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target_name(target));
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return result;
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}
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command_print(CMD, "%s: Invalidate instruction cache...done",
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target_name(target));
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} else {
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if (icache->line_size == 0)
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command_print(CMD, "%s: No instruction cache",
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target_name(target));
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else
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command_print(CMD, "%s: Instruction cache disabled",
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target_name(target));
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}
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} else
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command_print(CMD, "No valid parameter");
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}
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_icache_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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struct aice_port_s *aice = target_to_aice(target);
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struct nds32_cache *icache = &(nds32->memory.icache);
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int result;
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (icache->line_size == 0) {
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command_print(CMD, "%s: No instruction cache",
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target_name(target));
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return ERROR_OK;
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}
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if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
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if (icache->enable == true) {
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/* I$ invalidate */
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result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
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if (result != ERROR_OK) {
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command_print(CMD, "%s: Invalidate instruction cache...failed",
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target_name(target));
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return result;
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}
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command_print(CMD, "%s: Invalidate instruction cache...done",
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target_name(target));
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} else {
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command_print(CMD, "%s: Instruction cache disabled",
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target_name(target));
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}
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} else if (strcmp(CMD_ARGV[0], "enable") == 0) {
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uint32_t value;
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nds32_get_mapped_reg(nds32, IR8, &value);
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nds32_set_mapped_reg(nds32, IR8, value | 0x1);
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} else if (strcmp(CMD_ARGV[0], "disable") == 0) {
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uint32_t value;
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nds32_get_mapped_reg(nds32, IR8, &value);
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nds32_set_mapped_reg(nds32, IR8, value & ~0x1);
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} else if (strcmp(CMD_ARGV[0], "dump") == 0) {
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/* TODO: dump cache content */
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} else {
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command_print(CMD, "%s: No valid parameter", target_name(target));
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}
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}
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_dcache_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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struct aice_port_s *aice = target_to_aice(target);
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struct nds32_cache *dcache = &(nds32->memory.dcache);
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int result;
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (dcache->line_size == 0) {
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command_print(CMD, "%s: No data cache", target_name(target));
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return ERROR_OK;
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}
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if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
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if (dcache->enable == true) {
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/* D$ write back */
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result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
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if (result != ERROR_OK) {
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command_print(CMD, "%s: Write back data cache...failed",
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target_name(target));
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return result;
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}
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command_print(CMD, "%s: Write back data cache...done",
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target_name(target));
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/* D$ invalidate */
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result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
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if (result != ERROR_OK) {
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command_print(CMD, "%s: Invalidate data cache...failed",
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target_name(target));
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return result;
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}
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command_print(CMD, "%s: Invalidate data cache...done",
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target_name(target));
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} else {
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command_print(CMD, "%s: Data cache disabled",
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target_name(target));
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}
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} else if (strcmp(CMD_ARGV[0], "enable") == 0) {
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uint32_t value;
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nds32_get_mapped_reg(nds32, IR8, &value);
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nds32_set_mapped_reg(nds32, IR8, value | 0x2);
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} else if (strcmp(CMD_ARGV[0], "disable") == 0) {
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uint32_t value;
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nds32_get_mapped_reg(nds32, IR8, &value);
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nds32_set_mapped_reg(nds32, IR8, value & ~0x2);
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} else if (strcmp(CMD_ARGV[0], "dump") == 0) {
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/* TODO: dump cache content */
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} else {
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command_print(CMD, "%s: No valid parameter", target_name(target));
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}
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}
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_auto_break_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (strcmp(CMD_ARGV[0], "on") == 0)
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nds32->auto_convert_hw_bp = true;
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if (strcmp(CMD_ARGV[0], "off") == 0)
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nds32->auto_convert_hw_bp = false;
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}
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if (nds32->auto_convert_hw_bp)
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command_print(CMD, "%s: convert sw break to hw break on ROM: on",
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target_name(target));
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else
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command_print(CMD, "%s: convert sw break to hw break on ROM: off",
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target_name(target));
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_virtual_hosting_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (strcmp(CMD_ARGV[0], "on") == 0)
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nds32->virtual_hosting = true;
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if (strcmp(CMD_ARGV[0], "off") == 0)
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nds32->virtual_hosting = false;
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}
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if (nds32->virtual_hosting)
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command_print(CMD, "%s: virtual hosting: on", target_name(target));
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else
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command_print(CMD, "%s: virtual hosting: off", target_name(target));
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_global_stop_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (strcmp(CMD_ARGV[0], "on") == 0)
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nds32->global_stop = true;
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if (strcmp(CMD_ARGV[0], "off") == 0)
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nds32->global_stop = false;
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}
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if (nds32->global_stop)
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LOG_INFO("%s: global stop: on", target_name(target));
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else
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LOG_INFO("%s: global stop: off", target_name(target));
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_soft_reset_halt_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0) {
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if (strcmp(CMD_ARGV[0], "on") == 0)
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nds32->soft_reset_halt = true;
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if (strcmp(CMD_ARGV[0], "off") == 0)
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nds32->soft_reset_halt = false;
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}
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if (nds32->soft_reset_halt)
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LOG_INFO("%s: soft-reset-halt: on", target_name(target));
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else
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LOG_INFO("%s: soft-reset-halt: off", target_name(target));
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_boot_time_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 0)
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], nds32->boot_time);
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_login_edm_passcode_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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nds32->edm_passcode = strdup(CMD_ARGV[0]);
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return ERROR_OK;
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}
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COMMAND_HANDLER(handle_nds32_login_edm_operation_command)
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{
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struct target *target = get_current_target(CMD_CTX);
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struct nds32 *nds32 = target_to_nds32(target);
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if (!is_nds32(nds32)) {
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command_print(CMD, "current target isn't an Andes core");
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return ERROR_FAIL;
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}
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if (CMD_ARGC > 1) {
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uint32_t misc_reg_no;
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uint32_t data;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], misc_reg_no);
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], data);
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if (nds32_edm_ops_num >= NDS32_EDM_OPERATION_MAX_NUM)
|
|
return ERROR_FAIL;
|
|
|
|
/* Just save the operation. Execute it in nds32_login() */
|
|
nds32_edm_ops[nds32_edm_ops_num].reg_no = misc_reg_no;
|
|
nds32_edm_ops[nds32_edm_ops_num].value = data;
|
|
nds32_edm_ops_num++;
|
|
} else
|
|
return ERROR_FAIL;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct nds32 *nds32 = target_to_nds32(target);
|
|
|
|
if (!is_nds32(nds32)) {
|
|
command_print(CMD, "current target isn't an Andes core");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
if (CMD_ARGC > 0) {
|
|
if (strcmp(CMD_ARGV[0], "on") == 0)
|
|
nds32->reset_halt_as_examine = true;
|
|
if (strcmp(CMD_ARGV[0], "off") == 0)
|
|
nds32->reset_halt_as_examine = false;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct nds32 *nds32 = target_to_nds32(target);
|
|
|
|
if (!is_nds32(nds32)) {
|
|
command_print(CMD, "current target isn't an Andes core");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
if (CMD_ARGC > 0) {
|
|
if (strcmp(CMD_ARGV[0], "on") == 0)
|
|
nds32->keep_target_edm_ctl = true;
|
|
if (strcmp(CMD_ARGV[0], "off") == 0)
|
|
nds32->keep_target_edm_ctl = false;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_nds32_decode_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct nds32 *nds32 = target_to_nds32(target);
|
|
|
|
if (!is_nds32(nds32)) {
|
|
command_print(CMD, "current target isn't an Andes core");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
if (CMD_ARGC > 1) {
|
|
|
|
uint32_t addr;
|
|
uint32_t insn_count;
|
|
uint32_t opcode;
|
|
uint32_t read_addr;
|
|
uint32_t i;
|
|
struct nds32_instruction instruction;
|
|
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], insn_count);
|
|
|
|
read_addr = addr;
|
|
i = 0;
|
|
while (i < insn_count) {
|
|
if (nds32_read_opcode(nds32, read_addr, &opcode) != ERROR_OK)
|
|
return ERROR_FAIL;
|
|
if (nds32_evaluate_opcode(nds32, opcode, read_addr, &instruction) != ERROR_OK)
|
|
return ERROR_FAIL;
|
|
|
|
command_print(CMD, "%s", instruction.text);
|
|
|
|
read_addr += instruction.instruction_size;
|
|
i++;
|
|
}
|
|
} else if (CMD_ARGC == 1) {
|
|
|
|
uint32_t addr;
|
|
uint32_t opcode;
|
|
struct nds32_instruction instruction;
|
|
|
|
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
|
|
|
|
if (nds32_read_opcode(nds32, addr, &opcode) != ERROR_OK)
|
|
return ERROR_FAIL;
|
|
if (nds32_evaluate_opcode(nds32, opcode, addr, &instruction) != ERROR_OK)
|
|
return ERROR_FAIL;
|
|
|
|
command_print(CMD, "%s", instruction.text);
|
|
} else
|
|
return ERROR_FAIL;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_nds32_word_access_mem_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct nds32 *nds32 = target_to_nds32(target);
|
|
|
|
if (!is_nds32(nds32)) {
|
|
command_print(CMD, "current target isn't an Andes core");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
if (CMD_ARGC > 0) {
|
|
if (strcmp(CMD_ARGV[0], "on") == 0)
|
|
nds32->word_access_mem = true;
|
|
if (strcmp(CMD_ARGV[0], "off") == 0)
|
|
nds32->word_access_mem = false;
|
|
}
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_nds32_query_target_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct nds32 *nds32 = target_to_nds32(target);
|
|
|
|
if (!is_nds32(nds32)) {
|
|
command_print(CMD, "current target isn't an Andes core");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
command_print(CMD, "OCD");
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_nds32_query_endian_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct nds32 *nds32 = target_to_nds32(target);
|
|
|
|
if (!is_nds32(nds32)) {
|
|
command_print(CMD, "current target isn't an Andes core");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
uint32_t value_psw;
|
|
nds32_get_mapped_reg(nds32, IR0, &value_psw);
|
|
|
|
if (value_psw & 0x20)
|
|
command_print(CMD, "%s: BE", target_name(target));
|
|
else
|
|
command_print(CMD, "%s: LE", target_name(target));
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
COMMAND_HANDLER(handle_nds32_query_cpuid_command)
|
|
{
|
|
struct target *target = get_current_target(CMD_CTX);
|
|
struct nds32 *nds32 = target_to_nds32(target);
|
|
|
|
if (!is_nds32(nds32)) {
|
|
command_print(CMD, "current target isn't an Andes core");
|
|
return ERROR_FAIL;
|
|
}
|
|
|
|
command_print(CMD, "CPUID: %s", target_name(target));
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
|
|
{
|
|
const char *cmd_name = Jim_GetString(argv[0], NULL);
|
|
|
|
struct jim_getopt_info goi;
|
|
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
|
|
|
|
if (goi.argc < 3) {
|
|
Jim_SetResultFormatted(goi.interp,
|
|
"usage: %s <address> <count> <data>", cmd_name);
|
|
return JIM_ERR;
|
|
}
|
|
|
|
int e;
|
|
jim_wide address;
|
|
e = jim_getopt_wide(&goi, &address);
|
|
if (e != JIM_OK)
|
|
return e;
|
|
|
|
jim_wide count;
|
|
e = jim_getopt_wide(&goi, &count);
|
|
if (e != JIM_OK)
|
|
return e;
|
|
|
|
uint32_t *data = malloc(count * sizeof(uint32_t));
|
|
if (!data)
|
|
return JIM_ERR;
|
|
|
|
jim_wide i;
|
|
for (i = 0; i < count; i++) {
|
|
jim_wide tmp;
|
|
e = jim_getopt_wide(&goi, &tmp);
|
|
if (e != JIM_OK) {
|
|
free(data);
|
|
return e;
|
|
}
|
|
data[i] = (uint32_t)tmp;
|
|
}
|
|
|
|
/* all args must be consumed */
|
|
if (goi.argc != 0) {
|
|
free(data);
|
|
return JIM_ERR;
|
|
}
|
|
|
|
struct command_context *cmd_ctx = current_command_context(interp);
|
|
assert(cmd_ctx);
|
|
struct target *target = get_current_target(cmd_ctx);
|
|
int result;
|
|
|
|
result = target_write_buffer(target, address, count * 4, (const uint8_t *)data);
|
|
|
|
free(data);
|
|
|
|
return result;
|
|
}
|
|
|
|
static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
|
|
{
|
|
const char *cmd_name = Jim_GetString(argv[0], NULL);
|
|
|
|
struct jim_getopt_info goi;
|
|
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
|
|
|
|
if (goi.argc < 3) {
|
|
Jim_SetResultFormatted(goi.interp,
|
|
"usage: %s # of pairs [<address> <data>]+", cmd_name);
|
|
return JIM_ERR;
|
|
}
|
|
|
|
int e;
|
|
jim_wide num_of_pairs;
|
|
e = jim_getopt_wide(&goi, &num_of_pairs);
|
|
if (e != JIM_OK)
|
|
return e;
|
|
|
|
struct command_context *cmd_ctx = current_command_context(interp);
|
|
assert(cmd_ctx);
|
|
struct target *target = get_current_target(cmd_ctx);
|
|
struct aice_port_s *aice = target_to_aice(target);
|
|
int result;
|
|
uint32_t address;
|
|
uint32_t data;
|
|
jim_wide i;
|
|
|
|
aice_set_command_mode(aice, AICE_COMMAND_MODE_PACK);
|
|
for (i = 0; i < num_of_pairs; i++) {
|
|
jim_wide tmp;
|
|
e = jim_getopt_wide(&goi, &tmp);
|
|
if (e != JIM_OK)
|
|
break;
|
|
address = (uint32_t)tmp;
|
|
|
|
e = jim_getopt_wide(&goi, &tmp);
|
|
if (e != JIM_OK)
|
|
break;
|
|
data = (uint32_t)tmp;
|
|
|
|
result = target_write_buffer(target, address, 4, (const uint8_t *)&data);
|
|
if (result != ERROR_OK)
|
|
break;
|
|
}
|
|
aice_set_command_mode(aice, AICE_COMMAND_MODE_NORMAL);
|
|
|
|
/* all args must be consumed */
|
|
if (goi.argc != 0)
|
|
return JIM_ERR;
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
|
|
{
|
|
const char *cmd_name = Jim_GetString(argv[0], NULL);
|
|
|
|
struct jim_getopt_info goi;
|
|
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
|
|
|
|
if (goi.argc < 2) {
|
|
Jim_SetResultFormatted(goi.interp,
|
|
"usage: %s <address> <count>", cmd_name);
|
|
return JIM_ERR;
|
|
}
|
|
|
|
int e;
|
|
jim_wide address;
|
|
e = jim_getopt_wide(&goi, &address);
|
|
if (e != JIM_OK)
|
|
return e;
|
|
|
|
jim_wide count;
|
|
e = jim_getopt_wide(&goi, &count);
|
|
if (e != JIM_OK)
|
|
return e;
|
|
|
|
/* all args must be consumed */
|
|
if (goi.argc != 0)
|
|
return JIM_ERR;
|
|
|
|
struct command_context *cmd_ctx = current_command_context(interp);
|
|
assert(cmd_ctx);
|
|
struct target *target = get_current_target(cmd_ctx);
|
|
uint32_t *data = malloc(count * sizeof(uint32_t));
|
|
int result;
|
|
result = target_read_buffer(target, address, count * 4, (uint8_t *)data);
|
|
char data_str[12];
|
|
|
|
jim_wide i;
|
|
Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
|
|
for (i = 0; i < count; i++) {
|
|
sprintf(data_str, "0x%08" PRIx32 " ", data[i]);
|
|
Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
|
|
}
|
|
|
|
free(data);
|
|
|
|
return result;
|
|
}
|
|
|
|
static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
|
|
{
|
|
const char *cmd_name = Jim_GetString(argv[0], NULL);
|
|
|
|
struct jim_getopt_info goi;
|
|
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
|
|
|
|
if (goi.argc < 1) {
|
|
Jim_SetResultFormatted(goi.interp,
|
|
"usage: %s <edm_sr_name>", cmd_name);
|
|
return JIM_ERR;
|
|
}
|
|
|
|
int e;
|
|
const char *edm_sr_name;
|
|
int edm_sr_name_len;
|
|
e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len);
|
|
if (e != JIM_OK)
|
|
return e;
|
|
|
|
/* all args must be consumed */
|
|
if (goi.argc != 0)
|
|
return JIM_ERR;
|
|
|
|
uint32_t edm_sr_number;
|
|
uint32_t edm_sr_value;
|
|
if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
|
|
edm_sr_number = NDS_EDM_SR_EDM_DTR;
|
|
else if (strncmp(edm_sr_name, "edmsw", edm_sr_name_len) == 0)
|
|
edm_sr_number = NDS_EDM_SR_EDMSW;
|
|
else
|
|
return ERROR_FAIL;
|
|
|
|
struct command_context *cmd_ctx = current_command_context(interp);
|
|
assert(cmd_ctx);
|
|
struct target *target = get_current_target(cmd_ctx);
|
|
struct aice_port_s *aice = target_to_aice(target);
|
|
char data_str[11];
|
|
|
|
aice_read_debug_reg(aice, edm_sr_number, &edm_sr_value);
|
|
|
|
sprintf(data_str, "0x%08" PRIx32, edm_sr_value);
|
|
Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
|
|
Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
|
|
{
|
|
const char *cmd_name = Jim_GetString(argv[0], NULL);
|
|
|
|
struct jim_getopt_info goi;
|
|
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
|
|
|
|
if (goi.argc < 2) {
|
|
Jim_SetResultFormatted(goi.interp,
|
|
"usage: %s <edm_sr_name> <value>", cmd_name);
|
|
return JIM_ERR;
|
|
}
|
|
|
|
int e;
|
|
const char *edm_sr_name;
|
|
int edm_sr_name_len;
|
|
e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len);
|
|
if (e != JIM_OK)
|
|
return e;
|
|
|
|
jim_wide value;
|
|
e = jim_getopt_wide(&goi, &value);
|
|
if (e != JIM_OK)
|
|
return e;
|
|
|
|
/* all args must be consumed */
|
|
if (goi.argc != 0)
|
|
return JIM_ERR;
|
|
|
|
uint32_t edm_sr_number;
|
|
if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
|
|
edm_sr_number = NDS_EDM_SR_EDM_DTR;
|
|
else
|
|
return ERROR_FAIL;
|
|
|
|
struct command_context *cmd_ctx = current_command_context(interp);
|
|
assert(cmd_ctx);
|
|
struct target *target = get_current_target(cmd_ctx);
|
|
struct aice_port_s *aice = target_to_aice(target);
|
|
|
|
aice_write_debug_reg(aice, edm_sr_number, value);
|
|
|
|
return ERROR_OK;
|
|
}
|
|
|
|
static const struct command_registration nds32_query_command_handlers[] = {
|
|
{
|
|
.name = "target",
|
|
.handler = handle_nds32_query_target_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "",
|
|
.help = "reply 'OCD' for gdb to identify server-side is OpenOCD",
|
|
},
|
|
{
|
|
.name = "endian",
|
|
.handler = handle_nds32_query_endian_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "",
|
|
.help = "query target endian",
|
|
},
|
|
{
|
|
.name = "cpuid",
|
|
.handler = handle_nds32_query_cpuid_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "",
|
|
.help = "query CPU ID",
|
|
},
|
|
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
static const struct command_registration nds32_exec_command_handlers[] = {
|
|
{
|
|
.name = "dssim",
|
|
.handler = handle_nds32_dssim_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "['on'|'off']",
|
|
.help = "display/change $INT_MASK.DSSIM status",
|
|
},
|
|
{
|
|
.name = "mem_access",
|
|
.handler = handle_nds32_memory_access_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "['bus'|'cpu']",
|
|
.help = "display/change memory access channel",
|
|
},
|
|
{
|
|
.name = "mem_mode",
|
|
.handler = handle_nds32_memory_mode_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "['auto'|'mem'|'ilm'|'dlm']",
|
|
.help = "display/change memory mode",
|
|
},
|
|
{
|
|
.name = "cache",
|
|
.handler = handle_nds32_cache_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "['invalidate']",
|
|
.help = "cache control",
|
|
},
|
|
{
|
|
.name = "icache",
|
|
.handler = handle_nds32_icache_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "['invalidate'|'enable'|'disable'|'dump']",
|
|
.help = "icache control",
|
|
},
|
|
{
|
|
.name = "dcache",
|
|
.handler = handle_nds32_dcache_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "['invalidate'|'enable'|'disable'|'dump']",
|
|
.help = "dcache control",
|
|
},
|
|
{
|
|
.name = "auto_break",
|
|
.handler = handle_nds32_auto_break_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "['on'|'off']",
|
|
.help = "convert software breakpoints to hardware breakpoints if needed",
|
|
},
|
|
{
|
|
.name = "virtual_hosting",
|
|
.handler = handle_nds32_virtual_hosting_command,
|
|
.mode = COMMAND_ANY,
|
|
.usage = "['on'|'off']",
|
|
.help = "turn on/off virtual hosting",
|
|
},
|
|
{
|
|
.name = "global_stop",
|
|
.handler = handle_nds32_global_stop_command,
|
|
.mode = COMMAND_ANY,
|
|
.usage = "['on'|'off']",
|
|
.help = "turn on/off global stop. After turning on, every load/store "
|
|
"instructions will be stopped to check memory access.",
|
|
},
|
|
{
|
|
.name = "soft_reset_halt",
|
|
.handler = handle_nds32_soft_reset_halt_command,
|
|
.mode = COMMAND_ANY,
|
|
.usage = "['on'|'off']",
|
|
.help = "as issuing rest-halt, to use soft-reset-halt or not."
|
|
"the feature is for backward-compatible.",
|
|
},
|
|
{
|
|
.name = "boot_time",
|
|
.handler = handle_nds32_boot_time_command,
|
|
.mode = COMMAND_CONFIG,
|
|
.usage = "milliseconds",
|
|
.help = "set the period to wait after srst.",
|
|
},
|
|
{
|
|
.name = "login_edm_passcode",
|
|
.handler = handle_nds32_login_edm_passcode_command,
|
|
.mode = COMMAND_CONFIG,
|
|
.usage = "passcode",
|
|
.help = "set EDM passcode for secure MCU debugging.",
|
|
},
|
|
{
|
|
.name = "login_edm_operation",
|
|
.handler = handle_nds32_login_edm_operation_command,
|
|
.mode = COMMAND_CONFIG,
|
|
.usage = "misc_reg_no value",
|
|
.help = "add EDM operations for secure MCU debugging.",
|
|
},
|
|
{
|
|
.name = "reset_halt_as_init",
|
|
.handler = handle_nds32_reset_halt_as_init_command,
|
|
.mode = COMMAND_CONFIG,
|
|
.usage = "['on'|'off']",
|
|
.help = "reset halt as openocd init.",
|
|
},
|
|
{
|
|
.name = "keep_target_edm_ctl",
|
|
.handler = handle_nds32_keep_target_edm_ctl_command,
|
|
.mode = COMMAND_CONFIG,
|
|
.usage = "['on'|'off']",
|
|
.help = "Backup/Restore target EDM_CTL register.",
|
|
},
|
|
{
|
|
.name = "decode",
|
|
.handler = handle_nds32_decode_command,
|
|
.mode = COMMAND_EXEC,
|
|
.usage = "address icount",
|
|
.help = "decode instruction.",
|
|
},
|
|
{
|
|
.name = "word_access_mem",
|
|
.handler = handle_nds32_word_access_mem_command,
|
|
.mode = COMMAND_ANY,
|
|
.usage = "['on'|'off']",
|
|
.help = "Always use word-aligned address to access memory.",
|
|
},
|
|
{
|
|
.name = "bulk_write",
|
|
.jim_handler = jim_nds32_bulk_write,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Write multiple 32-bit words to target memory",
|
|
.usage = "address count data",
|
|
},
|
|
{
|
|
.name = "multi_write",
|
|
.jim_handler = jim_nds32_multi_write,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Write multiple addresses/words to target memory",
|
|
.usage = "num_of_pairs [address data]+",
|
|
},
|
|
{
|
|
.name = "bulk_read",
|
|
.jim_handler = jim_nds32_bulk_read,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Read multiple 32-bit words from target memory",
|
|
.usage = "address count",
|
|
},
|
|
{
|
|
.name = "read_edmsr",
|
|
.jim_handler = jim_nds32_read_edm_sr,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Read EDM system register",
|
|
.usage = "['edmsw'|'edm_dtr']",
|
|
},
|
|
{
|
|
.name = "write_edmsr",
|
|
.jim_handler = jim_nds32_write_edm_sr,
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Write EDM system register",
|
|
.usage = "['edm_dtr'] value",
|
|
},
|
|
{
|
|
.name = "query",
|
|
.mode = COMMAND_EXEC,
|
|
.help = "Andes query command group",
|
|
.usage = "",
|
|
.chain = nds32_query_command_handlers,
|
|
},
|
|
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|
|
|
|
const struct command_registration nds32_command_handlers[] = {
|
|
{
|
|
.name = "nds",
|
|
.mode = COMMAND_ANY,
|
|
.help = "Andes command group",
|
|
.usage = "",
|
|
.chain = nds32_exec_command_handlers,
|
|
},
|
|
COMMAND_REGISTRATION_DONE
|
|
};
|