107 lines
2.4 KiB
C
107 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2013 Andes Technology *
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* Hsiangkai Wang <hkwang@andestech.com> *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_NDS32_EDM_H
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#define OPENOCD_TARGET_NDS32_EDM_H
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#include "helper/types.h"
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/**
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* @file
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* This is the interface to the Embedded Debug Module for Andes cores.
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*/
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/* EDM misc registers */
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enum nds_edm_misc_reg {
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NDS_EDM_MISC_DIMIR = 0x0,
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NDS_EDM_MISC_SBAR,
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NDS_EDM_MISC_EDM_CMDR,
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NDS_EDM_MISC_DBGER,
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NDS_EDM_MISC_ACC_CTL,
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NDS_EDM_MISC_EDM_PROBE,
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NDS_EDM_MISC_GEN_PORT0,
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NDS_EDM_MISC_GEN_PORT1,
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};
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/* EDM system registers */
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enum nds_edm_system_reg {
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NDS_EDM_SR_BPC0 = 0x00,
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NDS_EDM_SR_BPC1,
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NDS_EDM_SR_BPC2,
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NDS_EDM_SR_BPC3,
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NDS_EDM_SR_BPC4,
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NDS_EDM_SR_BPC5,
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NDS_EDM_SR_BPC6,
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NDS_EDM_SR_BPC7,
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NDS_EDM_SR_BPA0 = 0x08,
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NDS_EDM_SR_BPA1,
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NDS_EDM_SR_BPA2,
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NDS_EDM_SR_BPA3,
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NDS_EDM_SR_BPA4,
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NDS_EDM_SR_BPA5,
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NDS_EDM_SR_BPA6,
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NDS_EDM_SR_BPA7,
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NDS_EDM_SR_BPAM0 = 0x10,
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NDS_EDM_SR_BPAM1,
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NDS_EDM_SR_BPAM2,
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NDS_EDM_SR_BPAM3,
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NDS_EDM_SR_BPAM4,
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NDS_EDM_SR_BPAM5,
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NDS_EDM_SR_BPAM6,
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NDS_EDM_SR_BPAM7,
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NDS_EDM_SR_BPV0 = 0x18,
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NDS_EDM_SR_BPV1,
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NDS_EDM_SR_BPV2,
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NDS_EDM_SR_BPV3,
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NDS_EDM_SR_BPV4,
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NDS_EDM_SR_BPV5,
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NDS_EDM_SR_BPV6,
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NDS_EDM_SR_BPV7,
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NDS_EDM_SR_BPCID0 = 0x20,
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NDS_EDM_SR_BPCID1,
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NDS_EDM_SR_BPCID2,
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NDS_EDM_SR_BPCID3,
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NDS_EDM_SR_BPCID4,
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NDS_EDM_SR_BPCID5,
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NDS_EDM_SR_BPCID6,
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NDS_EDM_SR_BPCID7,
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NDS_EDM_SR_EDM_CFG = 0x28,
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NDS_EDM_SR_EDMSW = 0x30,
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NDS_EDM_SR_EDM_CTL = 0x38,
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NDS_EDM_SR_EDM_DTR = 0x40,
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NDS_EDM_SR_BPMTV = 0x48,
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NDS_EDM_SR_DIMBR = 0x50,
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NDS_EDM_SR_TECR0 = 0x70,
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NDS_EDM_SR_TECR1 = 0x71,
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};
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enum nds_memory_access {
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NDS_MEMORY_ACC_BUS = 0,
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NDS_MEMORY_ACC_CPU,
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};
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enum nds_memory_select {
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NDS_MEMORY_SELECT_AUTO = 0,
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NDS_MEMORY_SELECT_MEM = 1,
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NDS_MEMORY_SELECT_ILM = 2,
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NDS_MEMORY_SELECT_DLM = 3,
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};
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#define NDS_DBGER_DEX (0x1)
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#define NDS_DBGER_DPED (0x2)
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#define NDS_DBGER_CRST (0x4)
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#define NDS_DBGER_AT_MAX (0x8)
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#define NDS_DBGER_ILL_SEC_ACC (0x10)
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#define NDS_DBGER_ALL_SUPRS_EX (0x40000000)
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#define NDS_DBGER_RESACC (0x80000000)
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#define NDS_DBGER_CLEAR_ALL (0x1F)
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#define NDS_EDMSW_WDV (1 << 0)
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#define NDS_EDMSW_RDV (1 << 1)
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#endif /* OPENOCD_TARGET_NDS32_EDM_H */
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